A DC-link Capacitor Voltage Balancing with CMV Elimination using only the Switching State Redundancies for a Reduced Switch Count Multi-Level Inverter fed IM Drive

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control., using only inverter switching state redundancies. The proposed power circuit gives a simple power bits structure.

A ternary Schmitt trigger

A new ternary circuit, namely, a ternary Schmitt trigger, is presented. This novel circuit which is based on the well-known lambda diode, is suitable for integration using CMOS technology. The circuit has been simulated using the SPICE 2G Program. The results of the simulation are presented. The circuit offers a high degree of design flexibility. This circuit is expected to be a very useful functional block in the processing of ternary and pseudoternary signals.

A Simple Multiple Pulsewidth Modulated AC Choppe

A simple multiple pulsewidth modulated (MPWM) ac chopper using power transistors for 3-ý power control is discussed. 120ý chopping period is used for main transistors so that the circuit can accommodate resistive and lagging or leading power factor loads. Only 1-ý sensing is used for 3-ý control. An alternate economical power and control schemes for 3-ý MPWM ac choppers suitable only for resistive loads is also suggested. The experimental results for 12 choppings per cycle are given.

A Unique Filter-Preserver Device for Digital Photonic Circuits

We discuss micro ring resonator based optical logic gates using Kerr-type nonlinearity. Resonant wavelength selectivity is one key factor in achieving the desired gate. Based on basic gates like AND gate, OR gate etc. We proceed to propose a 3-bit binary adder circuit.Due to the presence of more than a single wavelength, the system gets complicated as we increase the number of components in the circuit. Hence it has been observed that for efficient designing and functioning of digital circuits in optical domain, we need a device which can give single wavelength output, filtering out all other wavelengths and at the same time preserve the digital characteristics of the output. We propose such filter-preserver device based on micro ring resonator.

A New PWM Control Method for Three-Phase Autosequentially Commutated Current Source Inverters

A new current pulsewidth modulation (PWM) method is presented which uses the principle of creating zero three-phase currents at selected instants of time, through which the load current harmonic content can be controlled along with the magnitude of its fundamental content. This gives rise to reduction of motor torque ripples through the selection of suitable PWM patterns and a fast current control in the inverter by varying the pulsewidths of the PWM pattern. Under this new PWM mode of operation, the autosequentially commutated inverter (ASCI) circuit can be modified easily so that a higher number of pulses can be accomodated within a half-cycle, compared to the normal ASCI circuit. The experimental oscillograms verify the effectiveness of the new PWM method.

High-Frequency Current Source Inverter

The frequency range of the current source inverter (CSI) is limited by the slow commutation process in the inverter circuit. A method to reduce the commutation time and to limit the commutation capacitor voltage is proposed. A brief description of the conventional CSI and a detailed analysis of the commutation intervals of the proposed circuit are given. The experimental waveforms observed in the laboratory verify the validity of the analysis.

Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop

In this paper, two new dual-path based area efficient loop filtercircuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 CSM analog process with 1.8V supply. The proposed circuits achievedup to 85% savings in capacitor area. Simulations showed goodmatch of the new circuits with the conventional circuit. Theproposed circuits are particularly useful in applications thatdemand low die area.

An apparatus for the study of switching characteristics in ferroelectrics

A circuit capable of producing bipolar square pulses of voltages up to +or-400 V, employing an integrated circuit timer and two mercury wetted relays is described. The frequency of the pulses can be varied from a cycle min-1 to 2 kHz. A variable temperature sample chamber and the temperature control and measurement circuits are also described. The performance of the circuit is evaluated using samples of TGS and NaNO2.

Protection and Switching-Aid Networks for Transistor Bridge Inverters

The present trend in the industry is towards the use of power transistors in the development of efficient Pulsewidth Modulated (PWM) inverters, because of their operation at high frequency, simplicity of turn-off, and low commutation losses compared to the technology using thyristors. But the protection of power transistors, minimization of switching power loss, and design of base drive circuit are very important for a reliable operation of the system. The requirements, analysis, and a simplified procedure for calculation of the switching-aid network components are presented. The transistor is protected against short circuit using a modified autoregulated and autoprotection drive circuit. The experimental results show that the switching power loss and voltage stress in the device can be reduced by suitable choice of the switching-aid network component values.

Modeling and analysis of energy quantization effects on single electron inverter performance

In this paper, for the first time, the effects of energy quantization on single electron transistor (SET) inverter performance are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly changes the Coulomb blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET inverter. A new analytical model for the noise margin of SET inverter is proposed which includes the energy quantization effects. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. A compact expression is developed for a novel parameter quantization threshold which is introduced for the first time in this paper. Quantization threshold explicitly defines the maximum energy quantization that an SET inverter logic circuit can withstand before its noise margin falls below a specified tolerance level. It is found that SET inverter designed with CT:CG=1/3 (where CT and CG are tunnel junction and gate capacitances, respectively) offers maximum robustness against energy quantization.

Thermal characterization of microheaters from the dynamic response

Thermal characterization of surface-micromachined microheaters is carried out from their dynamic response to electrothermal excitations. An electrical equivalent circuit model is developed for the thermo-mechanical system. The mechanical parameters are extracted from the frequency response obtained using a laser Doppler vibrometer. The resonant frequencies of the microheaters are measured and compared with FEM simulations. The thermal time constants are obtained from the electrical equivalent model by fitting the model response to the measured frequency response. Microheaters with an active area of 140 µm × 140 µm have been realized on two different layers (poly-1 and poly-2) with two different air gaps (2 µm and 2.75 µm). The effective time constants, combining thermal and mechanical responses, are in the range of 0.13–0.22 ms for heaters on the poly-1 layer and 1.9 µs–0.15 ms for microheaters on the poly-2 layer. The thermal time constants of the microheaters are in the range of a few microseconds, thus making them suitable for sensor applications that need a faster thermal response.

2 Algorithms For 3-Layer Channel Routing

A channel router is an important design aid in the design automation of VLSI circuit layout. Many algorithms have been developed based on various wiring models with routing done on two layers. With the recent advances in VLSI process technology, it is possible to have three independent layers for interconnection. In this paper two algorithms are presented for three-layer channel routing. The first assumes a very simple wiring model. This enables the routing problem to be solved optimally in a time of O(n log n). The second algorithm is for a different wiring model and has an upper bound of O(n2) for its execution time. It uses fewer horizontal tracks than the first algorithm. For the second model the channel width is not bounded by the channel density.

Pipeline Analog To Ternary Converter

The paper describes the application of the pipelining principle to the realization of an analogue-to-ternary converter. The circuit shows a considerable saving in hard-ware compared with an earlier proposed circuit. The main hardware components used are analogue comparators, subtractors and the delay elements; hence this method of A/T conversion can operate at a higher sampling frequency.

Simple period timing device for laser Doppler signals

A period timing device suitable for processing laser Doppler anemometer signals has been described here. The important features of this instrument are: it is inexpensive, simple to operate, and easy to fabricate. When the concentration of scattering particles is low the Doppler signal is in the form of a burst and the Doppler frequency is measured by timing the zero crossings of the signal. But the presence of noise calls for the use of validation criterion, and a 5–8 cycles comparison has been used in this instrument. Validation criterion requires the differential count between the 5 and 8 cycles to be multiplied by predetermined numbers that prescribe the accuracy of measurement. By choosing these numbers to be binary numbers, much simplification in circuit design has been accomplished since this permits the use of shift registers for multiplication. Validation accuracies of 1.6%, 3.2%, 6.3%, and 12.5% are possible with this device. The design presented here is for a 16-bit processor and uses TTL components. By substituting Schottky barrier TTLs the clock frequency can be increased from about 10 to 30 MHz resulting in an extension in the range of the instrument. Review of Scientific Instruments is copyrighted by The American Institute of Physics.

A Simple Multiple pulsewidth Modulated AC Multiple Chopper

A simple multiple pulsewidth modulated (MPWM) ac chopper using power transistors for 3-¿ power control is discussed. 120° chopping period is used for main transistors so that the circuit can accommodate resistive and lagging or leading power factor loads. Only 1-¿ sensing is used for 3-¿ control. An alternate economical power and control schemes for 3-¿ MPWM ac choppers suitable only for resistive loads is also suggested. The experimental results for 12 choppings per cycle are given.