Electric Field Directed Growth of Molecular Wires of Charge Transfer Molecules on Prefabricated Metal Electrodes

Molecular wires of charge transfer molecules were formed by co-evaporating the 7 7 8 8-Tetracyanoquinodimethane [TCNQ] (acceptor) and Tetrathiafulvalene [TTF] (donor) molecules across prefabricated metal electrodes. Molecular wires of TTF TCNQ were also formed by evaporating single complex of TTF:TCNQ across prefabricated metal electrodes The prefabricated metal electrodes were made using electron beam lithography on SiO2 and glass cover slip substrates. Even though TTF: TCNQ wires grown from both co-evaporation and evaporation techniques show semiconductor like behavior in temperature dependence of resistance they show different activation energies due the difference in stoichiometry of TTF and TCNQ.

Potential and Electric Field Profiles for Transmission line Insulators

Transmission of bulk power at high voltages over very long distances has become very imperative. At present, throughout the globe, this task has been mostly performed by overhead transmission lines. The dual task of mechanically supporting and electrically isolating the live phase conductors from the support tower is performed by string insulators. Whether in clean condition or under polluted conditions, the electrical stress distribution along the insulators governs the possible flashover, which is quite detrimental to the system. However, a reliable data on stress distribution in commonly employed string insulators are rather scarce. Considering this, the present work has made an attempt to study accurately, the field distribution in 220 kV strings for six different types of porcelain/ceramic insulators (Normal and Antifog discs) used for high voltage transmission. The surface charge simulation method is employed for the required field computation. Voltage and electric stress distribution is deduced and compared across different types of discs. A comparison on normalised surface resistance, which is an indicator for the stress concentration under polluted condition, is also attempted.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

V-Transform: “An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits

Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.

Fermion Electric Dipole Moments in R-parity violating Supersymmetry

In this talk I discuss some aspects of the study of electric dipole moments (EDMs) of the fermions, in the context of R-parity violating (\rpv) Supersymmetry (SUSY). I will start with a brief general discussion of how dipole moments, in general, serve as a probe of physics beyond the Standard Model (SM) and an even briefer summary of \rpv SUSY. I will follow by discussing a general method of analysis for obtaining the leading fermion mass dependence of the dipole moments and present its application to \rpv SUSY case. Then I will summarise the constraints that the analysis of $e,n$ and $Hg$ EDMs provide for the case of trilinear \rpv SUSY couplings and make a few comments on the case of bilinear \rpv, where the general method of analysis proposed by us does not work.

Extrinsic Analog Synthesis using Piecewise Linear Current-Mode Circuits

A methodology is presented for the synthesis of analog circuits using piecewise linear (PWL) approximations. The function to be synthesized is divided into PWL segments such that each segment can be realized using elementary MOS current-mode programmable-gain circuits. A number of these elementary current-mode circuits when connected in parallel, it is possible to realize piecewise linear approximation of any arbitrary analog function with in the allowed approximation error bounds. Simulation results show a close agreement between the desired function and the synthesized output. The number of PWL segments used for approximation and hence the circuit area is determined by the required accuracy and the smoothness of the resulting function.

Transient electric field distribution within the working volume of an NEMP simulator

Nuclear electro-magnetic pulse (NEMP) simulators which are used in the simulation of transient electromagnetic fields due to a high altitude nuclear detonation are generally excited with a double exponential high voltage pulse. This results in a current distribution on the wires of the simulator and hence a transient electric field in the working volume of the simulator where the test object is kept. It is found that for the simulator under study, the current distribution is non-uniform and so is the field distribution along the width of the simulator in the working volume. To make the current distribution uniform, several methods have been suggested and the results of these methods are analyzed and suitable conclusions are arrived at from those results.

Effect of substrate bias voltage on the structure, electric and dielectric properties of TiO(2) thin films by DC magnetron sputtering

Titanium dioxide (TiO(2)) films have been deposited on glass and p-silicon (1 0 0) substrates by DC magnetron sputtering technique to investigate their structural, electrical and optical properties. The surface composition of the TiO(2) films has been analyzed by X-ray photoelectron spectroscopy. The TiO(2) films formed on unbiased substrates were amorphous. Application of negative bias voltage to the substrate transformed the amorphous TiO(2) into polycrystalline as confirmed by Raman spectroscopic studies. Thin film capacitors with configuration of Al/TiO(2)/p-Si have been fabricated. The leakage current density of unbiased films was 1 x10(-6) A/cm(2) at a gate bias voltage of 1.5 V and it was decreased to 1.41 x 10(-7) A/cm(2) with the increase of substrate bias voltage to -150 V owing to the increase in thickness of interfacial layer of SiO(2). Dielectric properties and AC electrical conductivity of the films were studied at various frequencies for unbiased and biased at -150 V. The capacitance at 1 MHz for unbiased films was 2.42 x 10(-10) F and it increased to 5.8 x 10(-10) F in the films formed at substrate bias voltage of -150 V. Dielectric constant of TiO(2) films were calculated from capacitance-voltage measurements at 1 MHz frequency. The dielectric constant of unbiased films was 6.2 while those formed at -150 V it increased to 19. The optical band gap of the films decreased from 3.50 to 3.42 eV with the increase of substrate bias voltage from 0 to -150 V. (C) 2011 Elsevier B. V. All rights reserved.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.