Phonon scattering limited performance of monolayer MoS2 and WSe2 n-MOSFET

In this paper we show the effect of electron-phonon scattering on the performance of monolayer (1L) MoS2 and WSe2 channel based n-MOSFETs. Electronic properties of the channel materials are evaluated using the local density approximation (LDA) in density functional theory (DFT). For phonon dispersion we employ the small displacement / frozen phonon calculations in DFT. Thereafter using the non-equilibrium Green's function (NEGF) formalism, we study the effect of electron-phonon scattering and the contribution of various phonon modes on the performance of such devices. It is found that the performance of the WSe2 device is less impacted by phonon scattering, showing a ballisticity of 83% for 1L-WSe2 FET for channel length of 10 nm. Though 1L-MoS2 FET of similar dimension shows a lesser ballisticity of 75%. Also in the presence of scattering there exist a a 21-36% increase in the intrinsic delay time (tau) and a 10-18% reduction in peak transconductance (g(m)) for WSe2 and MoS2 devices respectively. (C) 2015 Author(s).

Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design

Dynamic power dissipation due to redundant switching is an important metric in data-path design. This paper focuses on the use of ingenious operand isolation circuits for low power design. Operand isolation attempts to reduce switching by clamping or latching the output of a first level of combinational circuit. This paper presents a novel method using power supply switching wherein both PMOS and NMOS stacks of a circuit are connected to the same power supply. Thus, the output gets clamped or latched to the power supply value with minimal leakage. The proposed circuits make use of only two transistors to clamp the entire Multiple Input Multiple Output (MIMO) block. Also, the latch-based designs have higher drive strength in comparison to the existing methods. Simulation results have shown considerable area reduction in comparison to the existing techniques without increasing timing overhead.

Gamma oscillations in the midbrain spatial attention network: linking circuits to function

Gamma-band (25-140 Hz) oscillations are ubiquitous in mammalian forebrain structures involved in sensory processing, attention, learning and memory. The optic tectum (01) is the central structure in a midbrain network that participates critically in controlling spatial attention. In this review, we summarize recent advances in characterizing a neural circuit in this midbrain network that generates large amplitude, space-specific, gamma oscillations in the avian OT, both in vivo and in vitro. We describe key physiological and pharmacological mechanisms that produce and regulate the structure of these oscillations. The extensive similarities between midbrain gamma oscillations in birds and those in the neocortex and hippocampus of mammals, offer important insights into the functional significance of a midbrain gamma oscillatory code.

A Simple Hysteretic Energy Harvesting Method for Nonneutral AC Switches in Load Automation

This paper presents a simple hysteretic method to obtain the energy required to operate the gate-drive, sensors, and other circuits within nonneutral ac switches intended for use in load automated buildings. The proposed method features a switch-mode low part-count self-powered MOSFET ac switch that achieves efficiency and load current THD figures comparable to those of an externally gate-driven switch built using similar MOSFETS. The fundamental operation of the method is explained in detail, followed by the modifications required for practical implementation. Certain design rules that allow the method to accommodate a wide range of single-phase loads from 10 VA to 1 kVA are discussed, along with an efficiency enhancement feature based on inherent MOSFET characteristics. The limitations and side effects of the method are also mentioned according to their levels of severity. Finally, experimental results obtained using a prototype sensor switch are presented, along with a performance comparison of the prototype with an externally gate-driven MOSFET switch.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Growth and electron effective mass measurements of strained Si and Si0.94Ge0.06 on relaxed Si0.62Ge0.38 buffers grown by rapid thermal chemical vapor deposition

Abstract: We report the growth and the electron cyclotron resonance measurements of n-type Si/Si0.62Ge0.38 and Si0.94Ge0.06/Si0.62Ge0.38 modulation-doped heterostructures grown by rapid thermal chemical vapor deposition. The strained Si and Si0.94Ge0.06 channels were grown on relaxed Si0.62Ge0.38 buffer layers, which consist of 0.6 mu m uniform Si0.62Ge0.38 layers and 0.5 mu m compositionally graded relaxed SiGe layers from 0 to 38% Ge. The buffer layers were annealed at 800 degrees C for 1 h to obtain complete relaxation. A 75 Angstrom Si(SiGe) channel with a 100 Angstrom spacer and a 300 Angstrom 2 X 10(19) cm(-3) n-type supply layer was grown on the top of the buffer layers. The cross-sectional transmission electron microscope reveals that the dense dislocation network is confined to the buffer layer, and relatively few dislocations terminate on the surface. The plan-view image indicates the threading dislocation density is about 4 X 10(6) cm(-2). The far-infrared measurements of electron cyclotron resonance were performed at 4 K with the magnetic field of 4-8 T. The effective masses determined from the slope of the center frequency of the absorption peak versus applied magnetic field plot are 0.203m(0) and 0.193m(0) for the two dimensional electron gases in the Si and Si0.94Ge0.06 channels, respectively. The Si effective mass is very close to that of a two dimensional electron gas in an Si MOSFET (0.198m(0)). The electron effective mass of Si0.94Ge0.06 is reported for the first time and is about 5% lower than that of pure Si.

Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors

As the conventional MOSFET's scaling is approaching the limit imposed by short channel effects, Double Gate (DG) MOS transistors are appearing as the most feasible candidate in terms of technology in sub-45nm technology nodes. As the short channel effect in DG transistor is controlled by the device geometry, undoped or lightly doped body is used to sustain the channel. There exits a disparity in threshold voltage calculation criteria of undoped-body symmetric double gate transistors which uses two definitions, one is potential based and the another is charge based definition. In this paper, a novel concept of "crossover point'' is introduced, which proves that the charge-based definition is more accurate than the potential based definition.The change in threshold voltage with body thickness variation for a fixed channel length is anomalous as predicted by potential based definition while it is monotonous for charge based definition.The threshold voltage is then extracted from drain currant versus gate voltage characteristics using linear extrapolation and "Third Derivative of Drain-Source Current'' method or simply "TD'' method. The trend of threshold voltage variation is found same in both the cases which support charge-based definition.

Analysis Of The Energy Quantization Effects On Single Electron Inverter Performance Through Noise Margin Modeling

Possible integration of Single Electron Transistor (SET) with CMOS technology is making the study of semiconductor SET more important than the metallic SET and consequently, the study of energy quantization effects on semiconductor SET devices and circuits is gaining significance. In this paper, for the first time, the effects of energy quantization on SET inverter performance are examined through analytical modeling and Monte Carlo simulations. It is observed that the primary effect of energy quantization is to change the Coulomb Blockade region and drain current of SET devices and as a result affects the noise margin, power dissipation, and the propagation delay of SET inverter. A new model for the noise margin of SET inverter is proposed which includes the energy quantization effects. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. It is shown that SET inverter designed with CT : CG = 1/3 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization.

On-Chip Clock Network Skew Measurement using Sub-Sampling

We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps.

A Note on the Genericity of Simultaneous Stabilizability and Pole Assignability

n this paper we study the genericity of simultaneous stabilizability, simultaneous strong stabilizability, and simultaneous pole assignability, in linear multivariable systems. The main results of the paper had been previously established by Ghosh and Byrnes using state-space methods. In contrast, the proofs in the present paper are based on input-output arguments, and are much simpler to follow, especially in the case of simultaneous and simultaneous strong stabilizability. Moreover, the input-output methods used here suggest computationally reliable algorithms for solving these two types of problems. In addition to the main results, we also prove some lemmas on generic greatest common divisors which are of independent interest.

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.

Analogue-to-quaternary converterst

This paper proposes two circuits for the realization of analogue-to-quaternary converters (AQCs) viz., pipeline AQC and circulation AQC. The proposed AQCs make use of three quaternary circuits namely four level comparator, multiplexer and D flip-flops. These circuits and also the relevant control circuits required in the realization of AQCs are described. A comparison of the two methods is made.

A ternary Schmitt trigger

A new ternary circuit, namely, a ternary Schmitt trigger, is presented. This novel circuit which is based on the well-known lambda diode, is suitable for integration using CMOS technology. The circuit has been simulated using the SPICE 2G Program. The results of the simulation are presented. The circuit offers a high degree of design flexibility. This circuit is expected to be a very useful functional block in the processing of ternary and pseudoternary signals.

Serial quaternary-to-analogue converters

Circuits for realizing serial quaternary-to-analogue converters (QACs) are proposed in this paper. Three techniques are presented based on Shannon-Rack decoder, sample/hold serial digital-to-analogue converter and cyclic digital-to-analogue converter. Circuits for the generation of control signals and the multiplexer required in the realization of the QACs are also described. A comparison of the three methods is made.

A simple firing delay control circuit for bridge converters

A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.