Analytical Evaluation of Squeeze Film Forces in a CMUT With Sealed Air-Filled Cavity

The presence of vacuum inside the cavity of a capacitive micromachined ultrasonic transducer (CMUT) causes the membrane of the device (which is the main vibrating structural component) to deflect towards the substrate, thereby causing a reduction in the effective gap height. This reduction causes a drastic decrease in the pull-in voltage of the device limiting the DC bias at which the device can be operated for maximum efficiency. In addition, this initial deflection of the membrane due to atmospheric pressure, causes significant stress stiffening of the the membrane, changing the natural frequency of the device significantly from the design value. To circumvent the deleterious effects of vacuum in the sealed cavity, we investigate the possibility of using sealed CMUT cavities with air inside at ambient pressure. In order to estimate the transducer loss due to the presence of air in the sealed cavity, we evaluate the resulting damping and determine the forces acting on the vibrating membrane resulting from the compression of the trapped air film. We take into account the flexure of the top vibrating membrane instead of assuming the motion to be parallel-plate like. Towards this end, we solve the linearized Reynolds equation using the appropriate boundary conditions and show that, for a sealed CMUT cavity, the presence of air does not cause any squeeze film damping.

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization

With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.

Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation

Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint. We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.

Process Variation Aware Estimation of Static Leakage Power in Nano-CMOS

We present a statistical methodology for leakage power estimation, due to subthreshold and gate tunneling leakage, in the presence of process variations, for 65 nm CMOS. The circuit leakage power variations is analyzed by Monte Carlo (MC) simulations, by characterizing NAND gate library. A statistical “hybrid model” is proposed, to extend this methodology to a generic library. We demonstrate that hybrid model based statistical design results in up to 95% improvement in the prediction of worst to best corner leakage spread, with an error of less than 0.5%, with respect to worst case design.

Design of a quadrotor micro air vehicle

In this paper, we present the design and development details of a micro air vehicle (MAV) built around a quadrotor configuration. A survey of implemented MAVs suggests that a quadrotor design has several advantages over other configurations, especially in the context of swarm intelligence applications. Our design approach consists of three stages. However, the focus of this paper is restricted to the first stage that involves selection of crucial components such as motor-rotor pair, battery source, and structural material. The application of MAVs are broad-ranging, from reconnaissance to search and rescue, and have immense potential in the rapidly advancing field of swarm intelligence.

Plane wave analysis of rectangular axial-inlet, axial-outlet and transverse-inlet, transverse-outlet air cleaners

In this work, one-dimensional flow-acoustic analysis of two basic configurations of air cleaners, (i) Rectangular Axial-Inlet, Axial-Outlet (RAIAO) and (ii) Rectangular Transverse-Inlet, Transverse-Outlet (RTITO), has been presented. This 1-D analytical approach has been verified with the help of 3-D FEM based software. Through subtraction of the acoustic performance of the bare plenum (without filter element) from that of the complete air cleaner box, the solitary performance of the filter element has been evaluated. Part of the present analysis illustrates that the analytical formulation remains effective even with offset positioning of the air pipes from the centre of the cross section of the air cleaner. The 1-D analytical tool computes much faster than its 3-D simulation counterpart. The present analysis not only predicts the acoustical impact of mean flow, but it also depicts the scenario with increased resistance of the filter element. Thus, the proposed 1-D analysis would help in the design of acoustically efficient air cleaners for automotive applications. (C) 2011 Institute of Noise Control Engineering.

Compiler Assisted Leakage Energy Optimization for Clustered VLIW Architectures

Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. Relatively simpler issue logic and the presence of a large number of function units in the VLIW and the clustered VLIW architectures attribute a large fraction of this leakage energy consumption in the functional units. However, functional units are not fully utilized in the VLIW architectures because of the inherent variations in the ILP of the programs. This underutilization is even more pronounced in the context of clustered VLIW architectures because of the contentions for the limited number of slow intercluster communication channels which lead to many short idle cycles.In the past, some architectural schemes have been proposed to obtain leakage energy bene .ts by aggressively exploiting the idleness of functional units. However, presence of many short idle cycles cause frequent transitions from the active mode to the sleep mode and vice-versa and adversely a ffects the energy benefits of a purely hardware based scheme. In this paper, we propose and evaluate a compiler instruction scheduling algorithm that assist such a hardware based scheme in the context of VLIW and clustered VLIW architectures. The proposed scheme exploits the scheduling slacks of instructions to orchestrate the functional unit mapping with the objective of reducing the number of transitions in functional units thereby keeping them off for a longer duration. The proposed compiler-assisted scheme obtains a further 12% reduction of energy consumption of functional units with negligible performance degradation over a hardware-only scheme for a VLIW architecture. The benefits are 15% and 17% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively. Our test bed uses the Trimaran compiler infrastructure.