Monoclonal antibodies in the study of architecture of plant viruses

Monoclonal antibodies have been used as probes to study the architecture of several plant viruses over the past decade. These studies complement the information obtained through X-ray crystallography and help in delineating epitopes on the surface of the virus. The monoclonal antibodies that recognize distinct epitopes also aid in unravelling the mechanisms of assembly/disassembly of virus particles. Group-specific and strain-specific monoclonal antibodies are widely used in the classification of viruses. The significant developments made in this emerging area are reviewed here with specific examples.

Estimation of elasticity map of soft biological tissue mimicking phantom using laser speckle contrast analysis

Scattering of coherent light from scattering particles causes phase shift to the scattered light. The interference of unscattered and scattered light causes the formation of speckles. When the scattering particles, under the influence of an ultrasound (US) pressure wave, vibrate, the phase shift fluctuates, thereby causing fluctuation in speckle intensity. We use the laser speckle contrast analysis (LSCA) to reconstruct a map of the elastic property (Young's modulus) of soft tissue-mimicking phantom. The displacement of the scatters is inversely related to the Young's modulus of the medium. The elastic properties of soft biological tissues vary, many fold with malignancy. The experimental results show that laser speckle contrast (LSC) is very sensitive to the pathological changes in a soft tissue medium. The experiments are carried out on a phantom with two cylindrical inclusions of sizes 6 mm in diameter, separated by 8 mm between them. Three samples are made. One inclusion has Young's modulus E of 40 kPa. The second inclusion has either a Young's modulus E of 20 kPa, or scattering coefficient of mu'(s), = 3.00 mm(-1) or absorption coefficient of mu(a) = 0.03 mm(-1). The optical absorption (mu(a)), reduced scattering (mu'(s)) coefficient, and the Young's modulus of the background are mu(a) = 0.01 mm(-1), mu'(s) = 1.00 mm(-1) and 12kPa, respectively. The experiments are carried out on all three phantoms. On a phantom with two inclusions of Young's modulus of 20 and 40 kPa, the measured relative speckle image contrasts are 36.55% and 63.72%, respectively. Experiments are repeated on phantoms with inclusions of mu(a) = 0.03 mm-1, E = 40 kPa and mu'(s) = 3.00 mm(-1). The results show that it is possible to detect inclusions with contrasts in optical absorption, optical scattering, and Young's modulus. Studies of the variation of laser speckle contrast with ultrasound driving force for various values of mu(a), mu'(s), and Young's modulus of the tissue mimicking medium are also carried out. (C) 2011 American Institute of Physics. doi:10.1063/1.3592352]

Propensity of formation of zipper architecture vs. Lincoln log arrangement in solvated molecular complexes of melamine with hydroxybenzoic acids

Molecular complexes of melamine with hydroxy and dihydroxybenzoic acids have been analyzed to assess the collective role of the hydroxyl (OH) and carboxyl (COOH) functionalities in the recognition process. In most cases, solvents of crystallization do play a major role in self-assembly and structure stabilization. Hydrated compounds generate linear chains of melamine molecules with acid molecules pendant resulting in a zipper architecture. However, anhydrous and solvated compounds generate tetrameric units consisting of melamine dimers together with acid molecules. These tetramers in turn interweave to form a Lincoln log arrangement in the crystal. The salt/co-crystal formation in these complexes cannot be predicted apriori on the basis of Delta pK(a) values as there exists a salt-to-co-crystal continuum.

Poly(lactic-co-glycolic acid): Carbon nanofiber composites for myocardial tissue engineering applications

The objective of the present in vitro research was to investigate cardiac tissue cell functions (specifically cardiomyocytes and neurons) on poly(lactic-co-glycolic acid) (PLGA) (50:50 wt.%)-carbon nanofiber (CNF) composites to ascertain their potential for myocardial tissue engineering applications. CNF were added to biodegradable PLGA to increase the conductivity and cytocompatibility of pure PLGA. For this reason, different PLGA:CNF ratios (100:0, 75:25, 50:50,25:75, and 0:100 wt.%) were used and the conductivity as well as cytocompatibility of cardiomyocytes and neurons were assessed. Scanning electron microscopy, X-ray diffraction and Raman spectroscopy analysis characterized the microstructure, chemistry, and crystallinity of the materials of interest to this study. The results show that PLGA:CNF materials are conductive and that the conductivity increases as greater amounts of CNF are added to PLGA, from OS m(-1) for pure PLGA (100:0 wt.%) to 5.5 x 10(-3) S m(-1) for pure CNF (0:100 wt.%). The results also indicate that cardiomyocyte density increases with greater amounts of CNF in PLGA (up to 25:75 wt.% PLGA:CNF) for up to 5 days. For neurons a similar trend to cardiomyocytes was observed, indicating that these conductive materials promoted the adhesion and proliferation of two cell types important for myocardial tissue engineering applications. This study thus provides, for the first time, an alternative conductive scaffold using nanotechnology which should be further explored for cardiovascular applications. (C) 2011 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved.

Dynamically Reconfigurable Regular Expression Matching Architecture

Regular Expressions are generic representations for a string or a collection of strings. This paper focuses on implementation of a regular expression matching architecture on reconfigurable fabric like FPGA. We present a Nondeterministic Finite Automata based implementation with extended regular expression syntax set compared to previous approaches. We also describe a dynamically reconfigurable generic block that implements the supported regular expression syntax. This enables formation of the regular expression hardware by a simple cascade of generic blocks as well as a possibility for reconfiguring the generic blocks to change the regular expression being matched. Further,we have developed an HDL code generator to obtain the VHDL description of the hardware for any regular expression set. Our optimized regular expression engine achieves a throughput of 2.45 Gbps. Our dynamically reconfigurable regular expression engine achieves a throughput of 0.8 Gbps using 12 FPGA slices per generic block on Xilinx Virtex2Pro FPGA.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

An optimal transform Architecture for H.264/AVC

This paper presents the design of the area optimized integer two dimensional discrete cosine transform (2-D DCT) used in H.264/AVC codecs. The 2-D DCT calculation is performed by utilizing the separability property, in such a way that 2-D DCT is divided into two 1-D DCT calculation that are joined through a common memory. Due to its area optimized approach, the design will find application in mobile devices. Verilog hardware description language (HDL) in cadence environment has been used for design, compilation, simulation and synthesis of transform block in 0.18 mu TSMC technology.

Modeling Architecture-OS interactions using Layered Queuing Network Models

The prevalent virtualization technologies provide QoS support within the software layers of the virtual machine monitor(VMM) or the operating system of the virtual machine(VM). The QoS features are mostly provided as extensions to the existing software used for accessing the I/O device because of which the applications sharing the I/O device experience loss of performance due to crosstalk effects or usable bandwidth. In this paper we examine the NIC sharing effects across VMs on a Xen virtualized server and present an alternate paradigm that improves the shared bandwidth and reduces the crosstalk effect on the VMs. We implement the proposed hardwaresoftware changes in a layered queuing network (LQN) model and use simulation techniques to evaluate the architecture. We find that simple changes in the device architecture and associated system software lead to application throughput improvement of up to 60%. The architecture also enables finer QoS controls at device level and increases the scalability of device sharing across multiple virtual machines. We find that the performance improvement derived using LQN model is comparable to that reported by similar but real implementations.

FREP: A Soft-Error Resilient Pipelined RISC Architecture

Soft error has become one of the major areas of attention with the device scaling and large scale integration. Lot of variants for superscalar architecture were proposed with focus on program re-execution, thread re-execution and instruction re-execution. In this paper we proposed a fault tolerant micro-architecture of pipelined RISC. The proposed architecture, Floating Resources Extended pipeline (FREP), re-executes the instructions using extended pipeline stages. The instructions are re-executed by hybrid architecture with a suitable combination of space and time redundancy.

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

Continous Time Sigma-Delta Modulator Employing a Novel Comparator Architecture

A novel comparator architecture is proposed for speed operation in low voltage environment. Performance comparison with a conventional regenerative comparator shows a speed-up of 41%. The proposed comparator is embedded in a continuous time sigma-delta ADC so as to reduce the quantizer delay and hence minimizes the excess loop delay problem. A performance enhancement of 1dB in the dynamic range of the ADC is achieved with this new comparator. We have implemented this ADC in a standard single-poly 8-Metal 0.13 mum UMC process. The entire system operates at 1.2 V supply providing a dynamic range of 32 dB consuming 720 muW of power and occupies an area of 0.1 mm2.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.