Characterization of lithium borate–bismuth tungstate glasses and glass-ceramics by impedance spectroscopy

Transparent glasses in the system (1−x)Li2B4O7–xBi2WO6 (0≤x≤0.35) were prepared via melt quenching technique. Differential thermal analysis was employed to characterize the as-quenched glasses. Glass-ceramics with high optical transparency were obtained by controlled heat-treatment of the glasses at 720 K for 6 h. The amorphous nature of the as-quenched glass and crystallinity of glass-ceramics were confirmed by X-ray powder diffraction studies. High resolution transmission electron microscopy (HRTEM) shows the presence of nearly spherical nanocrystallites of Bi2WO6 in Li2B4O7 glass matrix. Capacitance and dielectric loss measurements were carried out as a function of temperature (300–870 K) in the frequency range 100 Hz–40 MHz. Impedance spectroscopy employed to rationalize the electrical behavior of glasses and glass-ceramics suggest the coexistence of electronic and ionic conduction in these materials. The thermal activation energies for the electronic conduction and ionic conduction were also estimated based on the Arrhenius plots.

Indium Nitride Nanometric-Objects on c-Sapphire Grown by Plasma-Assisted Molecular Beam Epitaxy

The indium nitride (InN)-based nanometric-objects were grown directly on a c-sapphire substrate by using plasma-assisted molecular beam epitaxy (PAMBE) at different substrate temperatures. High resolution X-ray diffraction (HRXRD) reveals the InN (0002) reflection and full width at half maximum (FWHM) found to be decreased with increasing the growth temperature. The size, height and density of the grown nanometric-objects studied by scanning electron microscopy (SEM) has remarkable differences, evidencing the decisive role of substrate temperature. Photoluminescence (PL) studies revealed that the emission energy is shifted towards the higher side from the bulk value, i.e., a blue shift in the PL spectra was observed. The temperature dependence of the PL peak position shows an ``S-shaped'' emission energy shift, which can be attributed to the localization of carriers in the nanometric-objects.

VLSI Implementation of Spatial prediction Based Image Compression Scheme

We propose the design and implementation of hardware architecture for spatial prediction based image compression scheme, which consists of prediction phase and quantization phase. In prediction phase, the hierarchical tree structure obtained from the test image is used to predict every central pixel of an image by its four neighboring pixels. The prediction scheme generates an error image, to which the wavelet/sub-band coding algorithm can be applied to obtain efficient compression. The software model is tested for its performance in terms of entropy, standard deviation. The memory and silicon area constraints play a vital role in the realization of the hardware for hand-held devices. The hardware architecture is constructed for the proposed scheme, which involves the aspects of parallelism in instructions and data. The processor consists of pipelined functional units to obtain the maximum throughput and higher speed of operation. The hardware model is analyzed for performance in terms throughput, speed and power. The results of hardware model indicate that the proposed architecture is suitable for power constrained implementations with higher data rate

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Ballistic Studies on TiB2-Ti Functionally Graded Armor Ceramics

The objective of this paper is to discuss the results of the ballistic testing of spark plasma sintered TiB2-Ti based functionally graded materials (FGMs) with an aim to assess their performance in defeating small-calibre armor piercing projectiles. We studied the efficacy of FGM design and compared its ballistic properties with those of TiB2-based composites as well as other competing ceramic armors. The ballistic properties are critically analyzed in terms of depth of penetration, ballistic efficiency, fractographs of fractured surfaces as well as quantification of the shattered ceramic fragments. It was found that all the investigated ceramic compositions exhibit ballistic efficiency (eta) of 5.1 -5.9. We also found that by increasing the thickness of FGM from 5 mm to 7.8 mm, the ballistic property of the composite degraded. Also, the strength of the ceramic compositions studied is sufficient to completely fracture the nose of the pointed projectile used. Analysis of the ceramic fragments (2 mu m-10 mm) showed that harder the ceramic, coarser were the fragments formed. On comparing the results with available armor systems, it has been concluded that TiB2 based composites can show better ballistic properties, except B4C. SEM analysis of the fragments obtained after testing with FGM showed formation of cleavage steps as well as presence of intergranular cracks, indicating that the FGM fractured by mixed mode of failure. It can be concluded that the FGM developed has lower ballistic properties compared to its monolith TiB2-20 wt.% Ti.

MEMS based microactuator for microjet applications

The objective of this work is to confirm the possibility of utilization of PolyVinyliDeneFlouride (PVDF) films in MEMS based microactuator for microjet applications. A membrane type microactuator is designed, developed, packaged and tested. The microactuator consists of PVDF film attached to thin Silicon diaphragm. As the voltage difference is applied across it, due to the piezoelectric behaviour, it deforms primarily in d31 mode, which in turn deflects the diaphragm. Using finite element methods, coupled field analysis is carried out to optimize the dimensions of the actuator with respect to the output force and input voltage. A cavity with a square diaphragm of 1mm×1mm×5μm is realized using standard microfabrication technique. 50μm thick PVDF film, cut with special dicing saw, is glued inside the metalized cavity using low stress, conductive, room temperature cured epoxy. The 3mm×3mm×0.675mm actuator die is packaged using Chip-On-Board technique in conjunction with low temperature soldering for taking the connections. The micro-actuator is tested in both actuation and sensing mode. The developed actuator is proposed to use with micro nozzle to study the utilization in drug delivery system.

Synthesis, microstructure and thermal expansion studies on Ca0 center dot 5+x/2Sr0 center dot 5+x/2Zr4P6-2x Si-2x O-24 system prepared by co-precipitation method

We report on the synthesis, microstructure and thermal expansion studies on Ca0 center dot 5 + x/2Sr0 center dot 5 + x/2Zr4P6 -aEuro parts per thousand 2x Si-2x O-24 (x = 0 center dot 00 to 1 center dot 00) system which belongs to NZP family of low thermal expansion ceramics. The ceramics synthesized by co-precipitation method at lower calcination and the sintering temperatures were in pure NZP phase up to x = 0 center dot 37. For x a parts per thousand yen 0 center dot 5, in addition to NZP phase, ZrSiO4 and Ca2P2O7 form as secondary phases after sintering. The bulk thermal expansion behaviour of the members of this system was studied from 30 to 850 A degrees C. The thermal expansion coefficient increases from a negative value to a positive value with the silicon substitution in place of phosphorous and a near zero thermal expansion was observed at x = 0 center dot 75. The amount of hysteresis between heating and cooling curves increases progressively from x = 0 center dot 00 to 0 center dot 37 and then decreases for x > 0 center dot 37. The results were analysed on the basis of formation of the silicon based glassy phase and increase in thermal expansion anisotropy with silicon substitution.

Process control of cantilever deflection for sensor application based on optical waveguides

This paper reports on the fabrication of cantilever silicon-on-insulator (SOI) optical waveguides and presents solutions to the challenges of using a very thin 260-nm active silicon layer in the SOI structure to enable single-transverse-mode operation of the waveguide with minimal optical transmission losses. In particular, to ameliorate the anchor effect caused by the mean stress difference between the active silicon layer and buried oxide layer, a cantilever flattening process based on Ar plasma treatment is developed and presented. Vertical deflections of 0.5 mu m for 70-mu m-long cantilevers are mitigated to within few nanometers. Experimental investigations of cantilever mechanical resonance characteristics confirm the absence of significant detrimental side effects. Optical and mechanical modeling is extensively used to supplement experimental observations. This approach can satisfy the requirements for on-chip simultaneous readout of many integrated cantilever sensors in which the displacement or resonant frequency changes induced by analyte absorption are measured using an optical-waveguide-based division multiplexed system.

Optical read-out scheme based on Grated Waveguide Cantilever cavity resonance for interrogation of cantilever sensor arrays

The design and analysis of an optical read-out scheme based on a grated waveguide (GWG) resonator for interrogating microcantilever sensor arrays is presented. The optical system consisting of a micro cantilever monolithically integrated in proximity to a grated waveguide (GWG), is realized in silicon optical bench platform. The mathematical analysis of the optical system is performed using a Fabry-Perot interferometer model with a lossy cavity formed between the cantilever and the GWG and an analytical expression is derived for the optical power transmission as a function of the cantilever deflection which corresponds to cavity width variation. The intensity transmission of the optical system for different cantilever deflections estimated using the analytical expression captures the essential features exhibited by a FDTD numerical model.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Transfer free suspended graphene devices on silicon using electrodeposited copper

Transfer free processes using Cu films greatly simplify the fabrication of reliable suspended graphene devices. In this paper, the authors report on the use of electrodeposited Cu films on Si for transfer free fabrication of suspended graphene devices. The quality of graphene layers on optimized electrodeposited Cu and Cu foil are found to be the same. By selectively etching the underlying Cu, the authors have realized by a transfer free process metal contacted, suspended graphene beams up to 50 mu m in length directly on Si. The suspended graphene beams do not show any increase in defect levels over the as grown state indicating the efficiency of the transfer free process. Measured room temperature electronic mobilities of up to 5200 cm(2)/V.s show that this simpler and CMOS compatible route has the potential to replace the foil based route for such suspended nano and micro electromechanical device arrays. (C) 2014 American Vacuum Society.

Electronic band Structure and Photoemission Spectra of Graphene on Silicon Substrate

Synergizing graphene on silicon based nanostructures is pivotal in advancing nano-electronic device technology. A combination of molecular dynamics and density functional theory has been used to predict the electronic energy band structure and photo-emission spectrum for graphene-Si system with silicon as a substrate for graphene. The equilibrium geometry of the system after energy minimization is obtained from molecular dynamics simulations. For the stable geometry obtained, density functional theory calculations are employed to determine the energy band structure and dielectric constant of the system. Further the work function of the system which is a direct consequence of photoemission spectrum is calculated from the energy band structure using random phase approximations.

Ferroelectric and optical properties of Ba5Li2Ti2Nb8O30 ceramics potential for memory applications

Giant grained (42 mu m) translucent Ba5Li2Ti2Nb8O30 ceramic was fabricated by conventional sintering technique using the powders obtained via solid state reaction route. These samples were confirmed to possess tetragonal tungsten bronze structure (P4bm) at room temperature. The scanning electron microscopy established the average grain size to be close to 20 mu m. The photoluminescence studies carried out on these ceramics indicated sharp emission bands around 433 and 578 nm at an excitation wavelength of 350 nm which were attributed to band-edge emission as the band gap was 2.76 eV determined by Kubelka-Munk function. The dielectric properties of these ceramics were studied over wide frequency range (100-1 MHz) at room temperature. The decrease in dielectric constant with frequency could be explained on the basis of Koops theory. The dielectric constant and the loss were found to decrease with increasing frequency. The Curie temperature was confirmed to be similar to 370 A degrees C based on the dielectric anomaly observed when these measurements were carried out over a temperature range of 30-500 A degrees C. This shows a deviation from Curie-Weiss behaviour and hence an indicator of the occurrence of disordering in the system, the gamma = 1.23 which confirms the diffuse ferroelectric transition. These ceramics at room temperature exhibited P-E hysteresis loops, though not well saturated akin to that of their single crystalline counterparts. These are the suitable properties for ferroelectric random access memory applications.

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-path for realization of the such IEs. The IE synthesis methodology ensures maximal utilization of resources on the reconfigurable data-path. In this context we present the techniques used to realize IEs for applications that demand high throughput or those that must process data streams. The reconfigurable hardware called HyperCell comprises a reconfigurable execution fabric. The fabric is a collection of interconnected compute units. A typical use case of HyperCell is where it acts as a co-processor with a host and accelerates execution of IEs that are defined post-silicon. We demonstrate the effectiveness of our approach by evaluating the performance of some well-known integer kernels that are realized as IEs on HyperCell. Our methodology for realizing IEs through HyperCells permits overlapping of potentially all memory transactions with computations. We show significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path. (C) 2014 Elsevier B.V. All rights reserved.