Steady-State Stability of Current Mode Active-Clamp ZVS DC-DC Converters

Active-clamp dc-dc converters are pulsewidth-modulated converters having two switches featuring zero-voltage switching at frequencies beyond 100 kHz. Generalized equivalent circuits valid for steady-state and dynamic performance have been proposed for the family of active-clamp converters. The active-clamp converter is analyzed for its dynamic behavior under current control in this paper. The steady-state stability analysis is presented. On account of the lossless damping inherent in the active-clamp converters, it appears that the stability region in the current-controlled active-clamp converters get extended for duty ratios, a little greater than 0.5, unlike in conventional hard-switched converters. The conventional graphical approach fails to assess the stability of current-controlled active-clamp converters due to the coupling between the filter inductor current and resonant inductor current. An analysis that takes into account the presence of the resonant elements is presented to establish the condition for stability. This method correctly predicts the stability of the current-controlled active-clamp converters. A simple expression for the maximum duty cycle for subharmonic free operation is obtained. The results are verified experimentally.

A Computationally Efficient PWM Algorithm for Multilevel Inverters

Centred space vector PWM (CSVPWM) technique is popularly used for three level voltage source inverters. The reference voltage vector is synthesized by time-averaging of the three nearest voltage vectors produced by the inverter. Identifying the three voltage vectors, and calculation of the dwelling time for each vector are both computationally intensive. This paper analyses the process of PWM generation in CSVPWM. This analysis breaks up a three-level inverter into six different conceptual two level inverters in different regions of the fundamental cycle. Control of 3-level inverter is viewed as the control of the appropriate 2-level inverter. The analysis leads to a systematic simplification of the computations involved, finally resulting in a computationally efficient PWM algorithm. This algorithm exploits the equivalence between triangle comparison and space vector approaches to PWM generation. This algorithm does not involve any 3-phase/2-phase or 2-phase/3-phase transformation. This also does not involve any transformation from rectangular to polar coordinates, and vice versa. Further no evaluation of trigonometric functions is necessary. This algorithm also provides for the mitigation of DC neutral point unbalance, and is well suited to digital implementation. Simulation and experimental results are presented.

Decentralized Parallel Operation of Inverters Sharing Unbalanced and Nonlinear Loads

In this paper, a wireless control strategy for parallel operation of three-phase four-wire inverters is proposed. A generalized situation is considered where the inverters are of unequal power ratings and the loads are nonlinear and unbalanced in nature. The proposed control algorithm exploits the potential of sinusoidal domain proportional+multiresonant controller ( in the inner voltage regulation loop) to make the system suitable for nonlinear and unbalanced loads with a simple and generalized structure of virtual output-impedance loop. The decentralized operation is achieved by using three-phase P/Q droop characteristics. The overall control algorithm helps to limit the harmonic contents and the degree of unbalance in the output-voltage waveform and to achieve excellent power-sharing accuracy in spite of mismatch in the inverter output impedances. Moreover, a synchronized turn on with consequent change over to the droop mode is applied for the new incoming unit in order to limit the circulating current completely. The simulation and experimental results from-1 kVA and -0.5 kVA paralleled units validate the effectiveness of the scheme.

V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

Five-level inverter scheme for an open-end winding induction machine with less number of switches

Higher level of inversion is achieved with a less number of switches in the proposed scheme. The scheme proposes a five-level inverter for an open-end winding induction motor which uses only two DC-link rectifiers of voltage rating of Vdc/4, a neutral-point clamped (NPC) three-level inverter and a two-level inverter. Even though the two-level inverter is connected to the high-voltage side, it is always in square-wave operation. Since the two-level inverter is not switching in a pulse width modulated fashion and the magnitude of switching transient is only half compared to the convention three-level NPC inverter, the switching losses and electromagnetic interference is not so high. The scheme is experimentally verified on a 2.5 kW induction machine.

Common mode DC bus filter for Active Front-End converter

Active Front-End (AFE) converter operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Filter topologies for DC bus have to deal problems with switching frequency and harmonic currents. The proposed filter approach reduces common mode voltage and circulates third harmonic current within the system, resulting in minimal ground current injection. The filtering technique, its constrains and design to attenuate common mode voltage and eliminate lower order harmonics injection to ground is discussed. The experimental results for operation of the converter with both SPWM and CSVPWM are presented.

Evaluation and improvement of total transfer capability - A case study

With deregulation, the total transfer capability (TTC) calculation, which is the basis for evaluating available transfer capability (ATC), has become very significant. TTC is an important index in power markets with large volume of inter-area power exchanges and wheeling transactions taking place on an hourly basis. Its computation helps to achieve a viable technical and commercial transmission operation. The aim of the paper is to evaluate TTC in the interconnections and also to improve it using reactive optimization technique and UPFC devices. Computations are carried out for normal and contingency cases such as single line, tie line and generator outages. Base and optimized results are presented, and the results show how reactive optimization and unified power flow controller help to improve the system conditions. In this paper repeated power flow method is used to calculate TTC due to its ease of implementation. A case study is carried out on a 205 bus equivalent system, a part of Indian Southern grid. Parameters like voltage magnitude, L-index, minimum singular value and MW losses are computed to analyze the system performance.

An asymmetric cascaded H-Bridge inverters for generating 12-sided polygonal space vector diagrams for Motor drives

A new topology of asymmetric cascaded H-Bridge inverter is presented in this paper It consists of two cascaded H-bridge cells per phase. They are fed from isolated dc sources having a dc bus ratio of 1:0.366. Out of many space vectors possible from this circuit, only those are chosen that lie on 12-sided polygons. Thus, the overall space vector diagram produced by this circuit consists of multiple numbers of 12-sided polygons. With a proper PWM timing calculations based on these selected space vectors, it is possible to eliminate all the 6n +/- 1, (n = odd) harmonics from the phase voltage under all operating conditions. The switching frequency of individual H-Bridge cells is also substantially low. Extensive experimental results have been presented in this paper to validate the proposed concept.

A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating V(dc)/2 where V(dc) is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of V(dc)/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of V(dc)/2, switch less compared to the H-bridges, which operate at a lower voltage level of V(dc)/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions.

A five level inverter scheme with common mode volatge elimination by cascading conventional two level and three level NPC inverters for an induction motor drive

Common-mode voltage generated by the PWM inverter causes shaft voltage, bearing current and ground leakage current in induction motor drive system, resulting in an early motor failure. This paper presents a common-mode elimination scheme for a five-level inverter with reduced power circuit complexity. The proposed scheme is realised by cascading conventional two-level and conventional NPC three-level inverters in conjunction with an open-end winding three-phase induction motor drive and the common-mode voltage (CMV) elimination is achieved by using only switching states that result in zero CMV, for the entire modulation range.

A New Family of Soft Transition Converters: Design Example and Dynamic Model

The soft switching converters evolved through the resonant load, resonant switch, resonant transition and active clamp converters to eliminate switching losses in power converters. This paper briefly presents the operating principle of the new family of soft transition converters; the methodology of design of these converters is presented through an example. In the proposed family of converters, the switching transitions of both the main switch and auxiliary switch are lossless.When these converters are analysed in terms of the pole current and throw voltage, the defining equations of all converters belonging to this family become identical.Such a description allows one to define simple circuit oriented model for these converters. These circuit models help in evaluating the steady state and dynamic model of these converters. The standard dynamic performance functions of the converters are readily obtainable from this model. This paper presents these dynamic models and verifies the same through measurements on a prototype converter.

Digital Deadbeat Control Tuning for dc-dc Converters Using Error Correlation

This letter proposes a simple tuning algorithm for digital deadbeat control based on error correlation. By injecting a square-wave reference input and calculating the correlation of the control error, a gain correction for deadbeat control is obtained. The proposed solution is simple, it requires a short tuning time, and it is suitable for different DC-DC converter topologies. Simulation and experimental results on synchronous buck converters confirm the properties of the proposed tuning algorithm.