Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

Architecture of Run-time Reconfigurable Channel Decoder

Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

An Eventful Synthetic Approach Towards the Biologically Potent Natural Product Ottelione A: Enantio-, Regio- and Stereoselective Construction of the Bicyclic Core

A novel synthetic approach towards the recently reported anti-tumor and anti-tuberculor natural product ottelione A from the readily available Diels-Alder adduct of cyclopentadiene and p-benzoquinone is delineated. Our short strategy, besides being enantio-, regio- and stereoselective, charts an eventful course and is inherently well-suited for adaptation towards diverse synthetic analogues of this biologically potent natural product.

Facile hydrothermal synthesis and observation of bubbled growth mechanism in nano-ribbons aggregated microspherical Covellite blue-phosphor

Well uniform microspheres of phase pure Covellite were synthesized through a simple hydrothermal approach using poly vinyl pyrrolidone (PVP) as surfactant. The micro-spheres were constituted of numerous self-organized knitted nano-ribbons of similar to 30 nm thickness. The effect of conc. PVP in the hydrothermal precursor solution on the product morphology was investigated. Based on the out-coming product micro-architecture a growth mechanism was proposed which emphasized bubbled nucleation inside the hydrothermal reactor. In a comparative study on linear optical properties, enhancement of luminescent intensity was observed for nano-ribbon clung microspheres rather than that of agglomerates of distorted particles, which may be attributed to better crystallinity as well as reduced surface defects and ionic vacancies for ribbon-like nano-structures.

Parallel min-cut placement on reduced hardware SIMD architecture.

Massively parallel SIMD computing is applied to obtain an order of magnitude improvement in the executional speed of an important algorithm in VLSI design automation. The physical design of a VLSI circuit involves logic module placement as a subtask. The paper is concerned with accelerating the well known Min-cut placement technique for logic cell placement. The inherent parallelism of the Min-cut algorithm is identified, and it is shown that a parallel machine based on the efficient execution of the placement procedure.

Reinstate hydrogen peroxide as the product of alternative oxidase of plant mitochondria

Chill treatment of potato tubers for 8 days induced mitochondrial O-2 consumption by cyanide-insensitive alternative oxidase (AOX). About half of the total O-2 consumption in such mitochondria was found to be sensitive to salicylhydroxamate (SHAM), a known inhibitor of AOX activity. Addition of catalase to the reaction mixture of AOX during the reaction decreased the rate of SHAM-sensitive O-2 consumption by nearly half, and addition at the end of the reaction released half of the O-2 consumed by AOX, both typical of catalase action on H2O2. This reaffirmed that the product of reduction of O-2 by plant AOX was H2O2 as found earlier and not H2O as reported in some recent reviews.

A fault-tolerant multi-transputer architecture

A new fault-tolerant multi-transputer architecture capable of tolerating failure of any one component in the system is described. In the proposed architecture the processing nodes are automatically reconfigured in the event of a fault and the computations continue from the stage where the fault occurred. The process of reconfiguration is transparent to the user, and the identity of the failed component is communicated to the user along with the results of computations. Parallel solution of a typical engineering problem involving solution of Laplace's equation by the boundary element method has been implemented. The performance of the architecture in the event of faults has been investigated.

Architecture of Physalis Mottle Tymovirus as Probed by Monoclonal Antibodies and Cross-Linking Studies

Physalis mottle tymovirus (previously named belladonna mottle virus, Iowa strain) RNA was cross-linked to its coat protein by exposure of the intact virus to ultraviolet light. The site of cross-linking of the coat protein with the RNA was identified as Lys-10 by sequencing the oligonucleotide-linked tryptic peptide obtained upon HPLC separation subsequent to enzymetic digestion of the cross-linked and dissociated virus. Three monoclonal antibodies PA3B2, PB5G9, and PF12C9, obtained using denatured coat protein as antigen, cross-reacted effectively with the intact virus indicating that the epitopes recognized by these monoclonals are on the surface of the virus. Using the peptides generated by digestion with CNBr, clostripain, V-8 protease, or trypsin and a recombinant protein lacking the N-terminal 21 residues expressed from a cDNA clone, it was shown that PA3B2 recognizes the sequence 22-36 on the coat protein while PB5G9 and PF12C9 recognize region 75-110. These results suggest that Lys-10 is one of the specific sites through which the RNA interacts in the intact virus. The polypeptide segment (region 22-36) following this buried portion as well as the epitope within the region 75-110 are exposed in the intact virus. These observations are consistent with the canonical β-barrel structure observed in certain other plant viruses.