MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Hydrothermal synthesis of CdTe QDs: Their luminescence quenching in the presence of bio-molecules and observation of bistable memory effect in CdTe QD/PEDOT:PSS heterostructure

We report one-pot hydrothermal synthesis of nearly mono-disperse 3-mercaptopropionic acid capped water-soluble cadmium telluride (CdTe) quantum dots (QDs) using an air stable Te source. The optical and electrical characteristics were also studied here. It was shown that the hydrothermal synthesis could be tuned to synthesize nano structures of uniform size close to nanometers. The emissions of the CdTe QDs thus synthesized were in the range of 500-700 nm by varying the duration of synthesis. The full width at half maximum (FWHM) of the emission peaks is relatively narrow (40-90 nm), which indicates a nearly uniform distribution of QD size. The structural and optical properties of the QDs were characterized by transmission electron microscopy (TEM), photoluminescence (PL) and Ultraviolet-visible (UV-Vis) spectroscopy. The photoluminescence quenching of CdTe QDs in the presence of L-cysteine and DNA confirms its biocompatibility and its utility for biosensing applications. The room temperature current-voltage characteristics of QD film on ITO coated glass substrate show an electrically induced switching between states with high and low conductivities. The phenomenon is explained on the basis of charge confinement in quantum dots. (C) 2011 Elsevier B.V. All rights reserved.

High-temperature deformation processing maps for a NiTiCu shape memory alloy

The properties of widely used Ni-Ti-based shape memory alloys (SMAs) are highly sensitive to the underlying microstructure. Hence, controlling the evolution of microstructure during high-temperature deformation becomes important. In this article, the ``processing maps'' approach is utilized to identify the combination of temperature and strain rate for thermomechanical processing of a Ni(42)Ti(50)Cu(8) SMA. Uniaxial compression experiments were conducted in the temperature range of 800-1050 degrees C and at strain rate range of 10(-3) and 10(2) s(-1). Two-dimensional power dissipation efficiency and instability maps have been generated and various deformation mechanisms, which operate in different temperature and strain rate regimes, were identified with the aid of the maps and complementary microstructural analysis of the deformed specimens. Results show that the safe window for industrial processing of this alloy is in the range of 800-850 degrees C and at 0.1 s(-1), which leads to grain refinement and strain-free grains. Regions of the instability were identified, which result in strained microstructure, which in turn can affect the performance of the SMA.

Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.