High voltage DC power supply topology for pulsed load applications with converter switching synchronized to load pulses

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. This paper proposes a methodology to tackle the problems associated with this type of application. Synchronization of converter switching with load pulses enables the converter to switch at half the load switching frequency. Low switching frequency helps in ensuring safety of HV transformer insulation and reduction of losses due to skin and proximity effect. Phase-modulated series resonant converter with ZVS is used as the power converter.

Input voltage modulated high voltage DC power supply topology for pulsed load applications

High voltage power supplies for radar applications are investigated which are subjected to pulsed load with stringent specifications. In the proposed solution, power conversion is done in two stages. A low power-high frequency converter modulates the input voltage of a high power-low frequency converter. This method satisfies all the performance specifications and takes care of the critical aspects of HV transformer.

Some aids in the design of microstrip components II: Nomograms

Nomograms have been developed for coupled microstrips. With the help of these, it is possible to design various microstrip components. The design of a multiplexer using the directional filter is described and experimental results are given. Nomograms relating the even and odd mode impedances of coupled microstrip lines to the width to height rate and spacing to height ratio have been developed using the relations formulated by Schwarzmann. A multiplexer using directional filters is designed to operate with three channels at frequencies of 3÷3, 3÷4 and 3÷5 GHz and bandwidths of 10 MHz in each channel. Experimental results are given. The design specifications are satisfied reasonably well.

Validation of Decision Tables Used in Process Control

Process control rules may be specified using decision tables. Such a specification is superior when logical decisions to be taken in control dominate. In this paper we give a method of detecting redundancies, incompleteness, and contradictions in such specifications. Using such a technique thus ensures the validity of the specifications.

Aids in the design of microstrip components I: Getsinger's chart

Charts relating the capacitance to the width, spacing, thickness and height above the ground plane of coupled microstrips have been obtained. These are used to design hairpin line and hybrid hairpin line filters as well as multiplexers using microstrip comb line filters. The experimental results agree reasonably well with the design specifications. Getsinger's original charts for parallel coupled bars between parallel plates have been formulated for the microstrip case. Corresponding charts relating the capacitances to the width, spacing, thickness and height above the ground plane of coupled microstrips have been obtained. Examples of the use of these charts are shown in the design of hairpin lines and hybrid hairpin line filters as well as multiplexers using comb line filters. The hairpin line/hybrid hairpin line filters were designed to operate at a central frequency of 9÷5 GHz with 11 per cent bandwidth and 0÷5 dB ripple. The three filters constituting the comb line filters have center frequencies of 2÷4, 3÷0 and 3÷6 GHz. The components so designed were fabricated and tested. The dielectric used for the microstrip was teflon. Experimental curves for the attenuation (insertion loss) and VSWR are given. The design specifications arc satisfied quite well.

Beat frequency oscillations in the output voltage of high voltage DC power supplies under pulsed loading

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. Few converter topologies are proposed to tackle these problems. A study is made regarding the beat frequency oscillations that may exist with pulsed loading. It is illustrated with respect to the proposed converter topologies. Methods are proposed to eliminate or minimize these oscillations.

Evaluation of damage in reinforced concrete bridge beams using acoustic emission technique

Acoustic emission (AE) testing is a well-known method for damage identification of various concrete structures including bridges. This article presents a method to assess damage in reinforced concrete (RC) bridge beams subjected to incremental cyclic loading. The specifications in the standard NDIS-2421 were used to classify the damage in RC bridge beams. Earlier researchers classified the damage occurring in bridge beams by using crack mouth opening displacement (CMOD) and AE released and proposed a standard (NDIS-2421: the Japanese Society for NonDestructive Inspection). In general, multiple cracks take place in RC beams under bending; therefore, utilisation of CMOD for crack detection may not be appropriate. In the present study, the damage in RC beams is classified by using the AE released, deflection, strains in steel and concrete, because the measurement of the strains in steel and concrete is easy and the codes of practice are specified for different limit states (IS-456:2000). The observations made in the present experimental study have some important practical applications in assessing the state of damage of concrete structural members.

A spring-mass-lever model, stiffness and inertia maps for single-input, single-output compliant mechanisms

A spring-mass-lever (SML) model is introduced in this paper for a single-input-single-output compliant mechanism to capture its static and dynamic behavior. The SML model is a reduced-order model, and its five parameters provide physical insight and quantify the stiffness and inertia(1) at the input and output ports as well as the transformation of force and displacement between the input and output. The model parameters can be determined with reasonable accuracy without performing dynamic or modal analysis. The paper describes two uses of the SML model: computationally efficient analysis of a system of which the compliant mechanism is a part; and design of compliant mechanisms for the given user-specifications. During design, the SML model enables determining the feasible parameter space of user-specified requirements, assessing the suitability of a compliant mechanism to meet the user-specifications and also selecting and/or re-designing compliant mechanisms from an existing database. Manufacturing constraints, material choice, and other practical considerations are incorporated into this methodology. A micromachined accelerometer and a valve mechanism are used as examples to show the effectiveness of the SML model in analysis and design. (C) 2012 Published by Elsevier Ltd.

Row-buffer reorganization: simultaneously improving performance and reducing energy in DRAMs

In this paper, based on the temporal and spatial locality characteristics of memory accesses in multicores, we propose a re-organization of the existing single large row buffer in a DRAM bank into multiple smaller row-buffers. The proposed configuration helps improve the row hit rates and also brings down the energy required for row-activations. The major contribution of this work is proposing such a reorganization without requiring any significant changes to the existing widely accepted DRAM specifications. Our proposed reorganization improves performance by 35.8%, 14.5% and 21.6% in quad, eight and sixteen core workloads along with a 42%, 28% and 31% reduction in DRAM energy. Additionally, we introduce a Need Based Allocation scheme for buffer management that shows additional performance improvement.

Influence of strain localization on reliability based design of bridge abutments using pseudo-dynamic method

The paper focuses on reliability based design of bridge abutments when subjected to earthquake loading. Planar failure surface has been used in conjunction with pseudo-dynamic approach to compute the seismic active earth pressures on the bridge abutment. The proposed pseudo dynamic method, considers the effects of strain localization in the backfill soil and associated post-peak reduction in the shear resistance from peak to residual values along a previously formed failure plane, phase difference in shear waves and soil amplification along with the horizontal seismic accelerations. Four modes of stability viz. sliding, overturning, eccentricity and bearing capacity of the foundation soil are considered for the reliability analysis. The influence of various design parameters on the seismic reliability indices against four modes of failure is presented, following the suggestions of Japan Road Association, Caltrans Bridge Design Specifications and U.S Department of the Army.

Processing of enriched elemental boron (B-10 similar to 65 at. %)

Procedures were developed for purification and processing of electrodeposited enriched boron powder for control rod application in India's first commercial Proto Type Fast Breeder Reactor (PFBR). Methodology for removal of anionic (F-, Cl-, BF4-) and cationic (Fe2+, Fe3+, Ni2+) impurities was developed. Parameters for grinding boron flakes obtained after electrodeposition were optimized to obtain the boron powder having particle size less than 100 gm. The rate of removal of impurities was studied with respect to time and concentration of the reagents used for purification. Process parameters for grinding and removal of impurities were optimized. A flowsheet was proposed which helps in minimizing the purification time and concentration of the reagent used for the effective removal of impurities. The purification methodology developed in this work could produce boron that meets the technical specifications for control rod application in a fast reactor.

Low order anti-aliasing filters for sparse signals in embedded applications

Major emphasis, in compressed sensing (CS) research, has been on the acquisition of sub-Nyquist number of samples of a signal that has a sparse representation on some tight frame or an orthogonal basis, and subsequent reconstruction of the original signal using a plethora of recovery algorithms. In this paper, we present compressed sensing data acquisition from a different perspective, wherein a set of signals are reconstructed at a sampling rate which is a multiple of the sampling rate of the ADCs that are used to measure the signals. We illustrate how this can facilitate usage of anti-aliasing filters with relaxed frequency specifications and, consequently, of lower order.

Static analysis for checking data format compatibility of programs

Large software systems are developed by composing multiple programs. If the programs manip-ulate and exchange complex data, such as network packets or files, it is essential to establish that they follow compatible data formats. Most of the complexity of data formats is associated with the headers. In this paper, we address compatibility of programs operating over headers of network packets, files, images, etc. As format specifications are rarely available, we infer the format associated with headers by a program as a set of guarded layouts. In terms of these formats, we define and check compatibility of (a) producer-consumer programs and (b) different versions of producer (or consumer) programs. A compatible producer-consumer pair is free of type mismatches and logical incompatibilities such as the consumer rejecting valid outputs gen-erated by the producer. A backward compatible producer (resp. consumer) is guaranteed to be compatible with consumers (resp. producers) that were compatible with its older version. With our prototype tool, we identified 5 known bugs and 1 potential bug in (a) sender-receiver modules of Linux network drivers of 3 vendors and (b) different versions of a TIFF image library.

Membership models and the design of authentication protocols for MANETs

Authentication protocols are very much essential for secure communication in mobile ad hoc networks (MANETs). A number of authentication protocols for MANETs have been proposed in the literature which provide the basic authentication service while trying to optimize their performance and resource consumption parameters. A problem with most of these protocols is that the underlying networking environment on which they are applicable have been left unspecified. As a result, lack of specifications about the networking environments applicable to an authentication protocol for MANETs can mislead about the performance and the applicability of the protocol. In this paper, we first characterize networking environment for a MANET as its 'Membership Model' which is defined as a set of specifications related to the 'Membership Granting Server' (MGS) and the 'Membership Set Pattern' (MSP) of the MANET. We then identify various types of possible membership models for a MANET. In order to illustrate that while designing an authentication protocol for a MANET, it is very much necessary to consider the underlying membership model of the MANET, we study a set of six representative authentication protocols, and analyze their applicability for the membership models as enumerated in this paper. The analysis shows that the same protocol may not perform equally well in all membership models. In addition, there may be membership models which are important from the point of view of users, but for which no authentication protocol is available.

Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities

The twin demands of energy-efficiency and higher performance on DRAM are highly emphasized in multicore architectures. A variety of schemes have been proposed to address either the latency or the energy consumption of DRAMs. These schemes typically require non-trivial hardware changes and end up improving latency at the cost of energy or vice-versa. One specific DRAM performance problem in multicores is that interleaved accesses from different cores can potentially degrade row-buffer locality. In this paper, based on the temporal and spatial locality characteristics of memory accesses, we propose a reorganization of the existing single large row-buffer in a DRAM bank into multiple sub-row buffers (MSRB). This re-organization not only improves row hit rates, and hence the average memory latency, but also brings down the energy consumed by the DRAM. The first major contribution of this work is proposing such a reorganization without requiring any significant changes to the existing widely accepted DRAM specifications. Our proposed reorganization improves weighted speedup by 35.8%, 14.5% and 21.6% in quad, eight and sixteen core workloads along with a 42%, 28% and 31% reduction in DRAM energy. The proposed MSRB organization enables opportunities for the management of multiple row-buffers at the memory controller level. As the memory controller is aware of the behaviour of individual cores it allows us to implement coordinated buffer allocation schemes for different cores that take into account program behaviour. We demonstrate two such schemes, namely Fairness Oriented Allocation and Performance Oriented Allocation, which show the flexibility that memory controllers can now exploit in our MSRB organization to improve overall performance and/or fairness. Further, the MSRB organization enables additional opportunities for DRAM intra-bank parallelism and selective early precharging of the LRU row-buffer to further improve memory access latencies. These two optimizations together provide an additional 5.9% performance improvement.