64 resultados para Software testing. Test generation. Grammars


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The determination of consolidation characteristics forms an important aspect in the design of foundations and other earth-retaining structures. The conventional consolidation test as originally proposed by Teaaghi takes considerable time (more than 15 days in highly compressible soils with low coefficient of consolidation) and effort. Any effort to reduce the duration of testing will be desirable from several considerations. In this paper, an attempt has been made to propose a rapid method of consolidation testing. In the proposed method, the next load increment is applied as soon as the necessary time required to identify the percent consolidation is reached and to evaluate the coefficient of consolidation by one of the popular curve-fitting procedures. The rectangular hyperbola method has been used to identify the percent consolidation reached after any load increment, and to determine the coefficient of consolidation, before making the next load increment. The time required to complete the test using the rapid consolidation method could be as low as 4-5 h compared with 1 or 2 weeks in the case of the conventional consolidation test.

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The consistency of very soft sediments prevents the conventional oedometer test from being applied to study their compressibility and permeability characteristics. The hydraulic consolidation test in existence requires sophisticated instrumentation and testing procedures. The present paper proposes a seepage-force-induced consolidation testing procedure for studying the compressibility and permeability behavior of soft sediments at low effective stress levels. The good agreement that has been observed between the results obtained from the proposed method and the conventional oedometer test at overlapping effective stress levels indicates that the proposed method can be used to study the compressibility and permeability characteristics of soft sediments at low effective stress levels satisfactorily.

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Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

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Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

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Abstract—DC testing of parametric faults in non-linear analog circuits based on a new transformation, entitled, V-Transform acting on polynomial coefficient expansion of the circuit function is presented. V-Transform serves the dual purpose of monotonizing polynomial coefficients of circuit function expansion and increasing the sensitivity of these coefficients to circuit parameters. The sensitivity of V-Transform Coefficients (VTC) to circuit parameters is up to 3x-5x more than sensitivity of polynomial coefficients. As a case study, we consider a benchmark elliptic filter to validate our method. The technique is shown to uncover hitherto untestable parametric faults whose sizes are smaller than 10 % of the nominal values. I.

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Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint. We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.

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Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

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In achieving higher instruction level parallelism, software pipelining increases the register pressure in the loop. The usefulness of the generated schedule may be restricted to cases where the register pressure is less than the available number of registers. Spill instructions need to be introduced otherwise. But scheduling these spill instructions in the compact schedule is a difficult task. Several heuristics have been proposed to schedule spill code. These heuristics may generate more spill code than necessary, and scheduling them may necessitate increasing the initiation interval. We model the problem of register allocation with spill code generation and scheduling in software pipelined loops as a 0-1 integer linear program. The formulation minimizes the increase in initiation interval (II) by optimally placing spill code and simultaneously minimizes the amount of spill code produced. To the best of our knowledge, this is the first integrated formulation for register allocation, optimal spill code generation and scheduling for software pipelined loops. The proposed formulation performs better than the existing heuristics by preventing an increase in II in 11.11% of the loops and generating 18.48% less spill code on average among the loops extracted from Perfect Club and SPEC benchmarks with a moderate increase in compilation time.

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A geometric and non parametric procedure for testing if two finite set of points are linearly separable is proposed. The Linear Separability Test is equivalent to a test that determines if a strictly positive point h > 0 exists in the range of a matrix A (related to the points in the two finite sets). The algorithm proposed in the paper iteratively checks if a strictly positive point exists in a subspace by projecting a strictly positive vector with equal co-ordinates (p), on the subspace. At the end of each iteration, the subspace is reduced to a lower dimensional subspace. The test is completed within r ≤ min(n, d + 1) steps, for both linearly separable and non separable problems (r is the rank of A, n is the number of points and d is the dimension of the space containing the points). The worst case time complexity of the algorithm is O(nr3) and space complexity of the algorithm is O(nd). A small review of some of the prominent algorithms and their time complexities is included. The worst case computational complexity of our algorithm is lower than the worst case computational complexity of Simplex, Perceptron, Support Vector Machine and Convex Hull Algorithms, if d

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Simple algorithms have been developed to generate pairs of minterms forming a given 2-sum and thereby to test 2-asummability of switching functions. The 2-asummability testing procedure can be easily implemented on the computer. Since 2-asummability is a necessary and sufficient condition for a switching function of upto eight variables to be linearly separable (LS), it can be used for testing LS switching functions of upto eight variables.

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Editors' note:Flexible, large-area display and sensor arrays are finding growing applications in multimedia and future smart homes. This article first analyzes and compares current flexible devices, then discusses the implementation, requirements, and testing of flexible sensor arrays.—Jiun-Lang Huang (National Taiwan University) and Kwang-Ting (Tim) Cheng (University of California, Santa Barbara)

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Creep properties of QE22 magnesium based alloy and composites reinforced with 20 volume percent of short-fibers - Maftech (R), Saffil (R) or Supertech (R), were evaluated using the impression creep test. In the impression creep test, a load is applied with the help of a cylindrical tungsten carbide indenter of 1 mm diameter. This has advantages over conventional creep testing in terms of small specimen size requirement and simple machining. Depth of impression is recorded with time and steady state strain rate is obtained from the slope of the secondary strain (depth of impression divided by indenter diameter) vs. time plot. The results are compared with the creep obtained from conventional creep performed in tension on the same materials earlier. Microstructural examination of the plastically deformed regions is carried out to explain creep behaviour of these composites.

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This paper deals with the characterisation of tar from two configurations of bioresidue thermochemical conversion reactors designed for producer gas based power generation systems. The pulverised fuel reactor is a cyclone system (R1) and the solid bioresidue reactor (denoted R2) is an open top twin air entry system both at 75-90 kg/h capacity (to generate electricity similar to 100 kVA). The reactor, R2, has undergone rigorous test in a major Indo-Swiss programme for the tar quantity at various conditions. The former is a recent technology development. Tars collected from these systems by a standard tar collection apparatus at the laboratory at Indian Institute of Science have been analysed at the Royal Institute of Technology (KTH), Sweden. The results of these analyses show that these thermochemical conversion reactors behave differently from the earlier reactors reported in literature in so far as tar generation is concerned. The extent of tar in hot gas is about 700-800 ppm for R1 and 70-100 ppm for R2. The amounts of the major compounds - naphthalene and phenol-are much lower that what is generally understood to happen in the gasifiers in Europe. It is suggested that the longer residence times at high temperatures allowed for in these reactors is responsible for this behavior. It is concluded the new generation reactor concepts extensively tried out at lower power levels hold promise for high power atmospheric gasification systems for woody as well as pulverisable bioresidues.

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Electrical failure of insulation is known to be an extremal random process wherein nominally identical pro-rated specimens of equipment insulation, at constant stress fail at inordinately different times even under laboratory test conditions. In order to be able to estimate the life of power equipment, it is necessary to run long duration ageing experiments under accelerated stresses, to acquire and analyze insulation specific failure data. In the present work, Resin Impregnated Paper (RIP) a relatively new insulation system of choice used in transformer bushings, is taken as an example. The failure data has been processed using proven statistical methods, both graphical and analytical. The physical model governing insulation failure at constant accelerated stress has been assumed to be based on temperature dependent inverse power law model.