169 resultados para Integrated circuit layout


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We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

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A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.

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A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

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We report on the bacterial protein-based all-optical switches which operate at low laser power, high speed and fulfil most of the requirements to be an ideal all-optical switch without any moving parts involved. This consists of conventional optical waveguides coated with bacteriorhodopsin films at switching locations. The principle of operation of the switch is based on the light-induced refractive index change of bacteriorhodopsin. This approach opens the possibility of realizing proteinbased all-optical switches for communication network, integrated optics and optical computers.

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The StreamIt programming model has been proposed to exploit parallelism in streaming applications oil general purpose multicore architectures. The StreamIt graphs describe task, data and pipeline parallelism which can be exploited on accelerators such as Graphics Processing Units (GPUs) or CellBE which support abundant parallelism in hardware. In this paper, we describe a novel method to orchestrate the execution of if StreamIt program oil a multicore platform equipped with an accelerator. The proposed approach identifies, using profiling, the relative benefits of executing a task oil the superscalar CPU cores and the accelerator. We formulate the problem of partitioning the work between the CPU cores and the GPU, taking into account the latencies for data transfers and the required buffer layout transformations associated with the partitioning, as all integrated Integer Linear Program (ILP) which can then be solved by an ILP solver. We also propose an efficient heuristic algorithm for the work-partitioning between the CPU and the GPU, which provides solutions which are within 9.05% of the optimal solution on an average across the benchmark Suite. The partitioned tasks are then software pipelined to execute oil the multiple CPU cores and the Streaming Multiprocessors (SMs) of the GPU. The software pipelining algorithm orchestrates the execution between CPU cores and the GPU by emitting the code for the CPU and the GPU, and the code for the required data transfers. Our experiments on a platform with 8 CPU cores and a GeForce 8800 GTS 512 GPU show a geometric mean speedup of 6.94X with it maximum of 51.96X over it single threaded CPU execution across the StreamIt benchmarks. This is a 18.9% improvement over it partitioning strategy that maps only the filters that cannot be executed oil the GPU - the filters with state that is persistent across firings - onto the CPU.

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A simple linear ramp control circuit, suitable for use with force-commutated thyrister circuits is discussed here. The circuit is based on only two IM 558 dual timer iCs, operating from a single 15 V supply. The reset terminals facilitate inhibition of the output of any stage. The use of this circuit in a thyristor chopper operating at 400 Hz 13 described.

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A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

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On interrupting polarisation, the magnesium anode exhibits a negative overshoot in potential followed by a slow recovery to a steady state value. A model has been proposed to explain the opencircuit potential-time transient in terms of a spontaneous passivation of the metal and the consequent changes in the corrosion potential. Theoretical expressions have been derived for the timedependence of the open-circuit electrode potential. Calculated, potential-time curves thus obtained are in qualitative agreement with experimental data. A possible application of this phenomenon to develop non-destructive quality control tests of Mg, Li and Al-based dry cells has been pointed out.

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The recent trend towards minimizing the interconnections in large scale integration (LSI) circuits has led to intensive investigation in the development of ternary circuits and the improvement of their design. The ternary multiplexer is a convenient and useful logic module which can be used as a basic building block in the design of a ternary system. This paper discusses a systematic procedure for the simplification and realization of ternary functions using ternary multiplexers as building blocks. Both single level and multilevel multiplexing techniques are considered. The importance of the design procedure is highlighted by considering two specific applications, namely, the development of ternary adder/subtractor and TCD to ternary converter.

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An important limitation of the existing IGC algorithms, is that they do not explicitly exploit the inherent time scale separation that exist in aerospace vehicles between rotational and translational motions and hence can be ineffective. To address this issue, a two-loop partial integrated guidance and control (PIGC) scheme has been proposed in this paper. In this design, the outer loop uses a recently developed, computationally efficient, optimal control formulation named as model predictive static programming. It gives the commanded pitch and yaw rates whereas necessary roll-rate command is generated from a roll-stabilization loop. The inner loop tracks the outer loop commands using the Dynamic inversion philosophy. Uncommonly, Six-Degree of freedom (Six-DOF) model is used directly in both the loops. This intelligent manipulation preserves the inherent time scale separation property between the translational and rotational dynamics, and hence overcomes the deficiency of current IGC designs, while preserving its benefits. Comparative studies of PIGC with one loop IGC and conventional three loop design were carried out for engaging incoming high speed target. Simulation studies demonstrate the usefulness of this method.

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Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply, voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.

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During the course of preparation of a master plan for the transportation networks in Bangalore city, mapping the various initiatives and interventions planned towards addressing mobility, existing situation and implications of some of the proposed interventions was analysed. The inferences are based on existing transportation network; synthesis of various transportation related studies and proposed infrastructure initiatives (road works) in Bangalore. Broadly, they can be summarized as following five aspects: I. Need for ~Sreclassifying~T existing road networks (arterial and sub-arterial) with effective geospatial database in the back-end. II. The proposed Core Ring Road at surface grade may not be feasible. III. Current interventions encouraging more independent motorable transport by way of road widening, construction of underpasses, flyovers and grade-separators would not ease traffic congestion when addressed in isolation. IV. Factors affecting time and cost-overruns in infrastructure projects and ways to tackle are discussed. V. Initiatives required for addressing effective planning for operations recommended.

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A new 8-node serendipity quadrilateral plate bending element (MQP8) based on the Mindlin-Reissner theory for the analysis of thin and moderately thick plate bending problems using Integrated Force Method is presented in this paper. The performance of this new element (MQP8) is studied for accuracy and convergence by analyzing many standard benchmark plate bending problems. This new element MQP8 performs excellent in both thin and moderately thick plate bending situations. And also this element is free from spurious/zero energy modes and free from shear locking problem.

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The influence of electric field and temperature on power consumption of piezoelectric actuated integrated structure is studied by using a single degree of freedom mass-spring-damper system model coupled with a piezoactuator. The material lead zirconate titanate, is considered as it is capable of producing relatively high strains (e.g., 3000 mu epsilon). Actuators are often subject to high electric fields to increase the induced strain produced, resulting in field dependant piezoelectric coefficient d(31), dielectric coefficient epsilon(33) and dissipation factor delta. Piezostructures are also likely to be used across a wide range of temperatures in aerospace and undersea operations. Again, the piezoelectric properties can vary with temperature. Recent experimental studies by physics researchers have looked at the effect of high electric field and temperature on piezoelectric properties. These properties are used together with an impedance based power consumption model. Results show that including the nonlinear variation of dielectric permittivity and dissipation factor with electric field is important. Temperature dependence of the dielectric constant also should be considered.

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Optimal allocation of water resources for various stakeholders often involves considerable complexity with several conflicting goals, which often leads to multi-objective optimization. In aid of effective decision-making to the water managers, apart from developing effective multi-objective mathematical models, there is a greater necessity of providing efficient Pareto optimal solutions to the real world problems. This study proposes a swarm-intelligence-based multi-objective technique, namely the elitist-mutated multi-objective particle swarm optimization technique (EM-MOPSO), for arriving at efficient Pareto optimal solutions to the multi-objective water resource management problems. The EM-MOPSO technique is applied to a case study of the multi-objective reservoir operation problem. The model performance is evaluated by comparing with results of a non-dominated sorting genetic algorithm (NSGA-II) model, and it is found that the EM-MOPSO method results in better performance. The developed method can be used as an effective aid for multi-objective decision-making in integrated water resource management.