Paleoseismological evidence of surface faulting along the northeastern Himalayan front, India: Timing, size, and spatial extent of great earthquakes

The similar to 2500 km long Himalayan arc has experienced three large to great earthquakes of M-w 7.8 to 8.4 during the past century, but none produced surface rupture. Paleoseismic studies have been conducted during the last decade to begin understanding the timing, size, rupture extent, return period, and mechanics of the faulting associated with the occurrence of large surface rupturing earthquakes along the similar to 2500 km long Himalayan Frontal Thrust (HFT) system of India and Nepal. The previous studies have been limited to about nine sites along the western two-thirds of the HFT extending through northwest India and along the southern border of Nepal. We present here the results of paleoseismic investigations at three additional sites further to the northeast along the HFT within the Indian states of West Bengal and Assam. The three sites reside between the meizoseismal areas of the 1934 Bihar-Nepal and 1950 Assam earthquakes. The two westernmost of the sites, near the village of Chalsa and near the Nameri Tiger Preserve, show that offsets during the last surface rupture event were at minimum of about 14 m and 12 m, respectively. Limits on the ages of surface rupture at Chalsa (site A) and Nameri (site B), though broad, allow the possibility that the two sites record the same great historical rupture reported in Nepal around A.D. 1100. The correlation between the two sites is supported by the observation that the large displacements as recorded at Chalsa and Nameri would most likely be associated with rupture lengths of hundreds of kilometers or more and are on the same order as reported for a surface rupture earthquake reported in Nepal around A.D. 1100. Assuming the offsets observed at Chalsa and Nameri occurred synchronously with reported offsets in Nepal, the rupture length of the event would approach 700 to 800 km. The easternmost site is located within Harmutty Tea Estate (site C) at the edges of the 1950 Assam earthquake meizoseismal area. Here the most recent event offset is relatively much smaller (<2.5 m), and radiocarbon dating shows it to have occurred after A.D. 1100 (after about A.D. 1270). The location of the site near the edge of the meizoseismal region of the 1950 Assam earthquake and the relatively lesser offset allows speculation that the displacement records the 1950 M-w 8.4 Assam earthquake. Scatter in radiocarbon ages on detrital charcoal has not resulted in a firm bracket on the timing of events observed in the trenches. Nonetheless, the observations collected here, when taken together, suggest that the largest of thrust earthquakes along the Himalayan arc have rupture lengths and displacements of similar scale to the largest that have occurred historically along the world's subduction zones.

A Rotor Flux Estimation During Zero and Active Vector Periods Using Current Error Space Vector From a Hysteresis Controller for a Sensorless Vector Control of IM Drive

This paper proposes a sensorless vector control scheme for general-purpose induction motor drives using the current error space phasor-based hysteresis controller. In this paper, a new technique for sensorless operation is developed to estimate rotor voltage and hence rotor flux position using the stator current error during zero-voltage space vectors. It gives a comparable performance with the vector control drive using sensors especially at a very low speed of operation (less than 1 Hz). Since no voltage sensing is made, the dead-time effect and loss of accuracy in voltage sensing at low speed are avoided here, with the inherent advantages of the current error space phasor-based hysteresis controller. However, appropriate device on-state drops are compensated to achieve a steady-state operation up to less than 1 Hz. Moreover, using a parabolic boundary for current error, the switching frequency of the inverter can be maintained constant for the entire operating speed range. Simple sigma L-s estimation is proposed, and the parameter sensitivity of the control scheme to changes in stator resistance, R-s is also investigated in this paper. Extensive experimental results are shown at speeds less than 1 Hz to verify the proposed concept. The same control scheme is further extended from less than 1 Hz to rated 50 Hz six-step operation of the inverter. Here, the magnetic saturation is ignored in the control scheme.

A current error space vector based hysteresis controller with constant switching frequency and simple online boundary computation for VSI fed IM drive

This paper proposes a simple current error space vector based hysteresis controller for two-level inverter fed Induction Motor (IM) drives. This proposed hysteresis controller retains all advantages of conventional current error space vector based hysteresis controllers like fast dynamic response, simple to implement, adjacent voltage vector switching etc. The additional advantage of this proposed hysteresis controller is that it gives a phase voltage frequency spectrum exactly similar to that of a constant switching frequency space vector pulse width modulated (SVPWM) inverter. In this proposed hysteresis controller the boundary is computed online using estimated stator voltages along alpha and beta axes thus completely eliminating look up tables used for obtaining parabolic hysteresis boundary proposed in. The estimation of stator voltage is carried out using current errors along alpha and beta axes and steady state model of induction motor. The proposed scheme is simple and capable of taking inverter upto six step mode operation, if demanded by drive system. The proposed hysteresis controller based inverter fed drive scheme is simulated extensively using SIMULINK toolbox of MATLAB for steady state and transient performance. The experimental verification for steady state performance of the proposed scheme is carried out on a 3.7kW IM.

Common mode DC bus filter for Active Front-End converter

Active Front-End (AFE) converter operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Filter topologies for DC bus have to deal problems with switching frequency and harmonic currents. The proposed filter approach reduces common mode voltage and circulates third harmonic current within the system, resulting in minimal ground current injection. The filtering technique, its constrains and design to attenuate common mode voltage and eliminate lower order harmonics injection to ground is discussed. The experimental results for operation of the converter with both SPWM and CSVPWM are presented.

A Novel VSI- and CSI-Fed Dual Stator Induction Motor Drive Topology for Medium-Voltage Drive Applications

A new configuration is proposed for high-power induction motor drives. The induction machine is provided with two three-phase stator windings with their axes in line. One winding is designed for higher voltage and is meant to handle the main (active) power. The second winding is designed for lower voltage and is meant to carry the excitation (reactive) power. The excitation winding is powered by an insulated-gate-bipolar-transistor-based voltage source inverter with an output filter. The power winding is fed by a load-commutated current source inverter. The commutation of thyristors in the load-commutated inverter (LCI) is achieved by injecting the required leading reactive power from the excitation inverter. The MMF harmonics due to the LCI current are also cancelled out by injecting a suitable compensating component from the excitation inverter, so that the electromagnetic torque of the machine is smooth. Results from a prototype drive are presented to demonstrate the concept.

A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating V(dc)/2 where V(dc) is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of V(dc)/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of V(dc)/2, switch less compared to the H-bridges, which operate at a lower voltage level of V(dc)/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions.

A Multilevel inverter structure with cascaded two level and three level inverters for IM drive with CMV elimination and DC link capacitor voltage balancing

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control, using only inverter switching state redundancies. The proposed power circuit gives a simple power bus structure.

A five level inverter scheme with common mode volatge elimination by cascading conventional two level and three level NPC inverters for an induction motor drive

Common-mode voltage generated by the PWM inverter causes shaft voltage, bearing current and ground leakage current in induction motor drive system, resulting in an early motor failure. This paper presents a common-mode elimination scheme for a five-level inverter with reduced power circuit complexity. The proposed scheme is realised by cascading conventional two-level and conventional NPC three-level inverters in conjunction with an open-end winding three-phase induction motor drive and the common-mode voltage (CMV) elimination is achieved by using only switching states that result in zero CMV, for the entire modulation range.

Regenerative Dynamometer with Vector Controlled Drive

This paper presents the topology selection, design steps, simulation studies, design verification, system fabrication and performance evaluation on an induction motor based dynamometer system. The control algorithm used the application is well known field oriented control or vector control. Position sensorless scheme is adopted to eliminate the encoder requirement. The dynamometer is rated for 3.7kW. It can be used to determine the speed–torque characteristics of any rotating system. The rotating system is to be coupled with the vector controlled drive and the required torque command is given from the latter. The experimental verification is carried out for an open loop v/f drive as a test rotating system and important test results are presented.

Calculation of the front part of the sonic boom signature for a Maneuvering aerofopil

The sonic boom at a large distance from its source consists of a leading shock, a trailing shock and a one parameter family of nonlinear wavefronts in between these shocks. A new ray theoretical method using a shock ray theory and a weakly nonlinear lay theory has been used to obtain the shock fronts and wavefronts respectively, for a maneuvering aerofoil in a homogeneous medium. This method introduces a one parameter family of Cauchy problems to calculate the shock and wave fronts emerging from the surface of the aerofoil. These problems are solved numerically to obtain the leading shock front and the nonlinear wavefronts emerging from the front portion of the aerofoil.

A power scalable receiver front-end at 2.4 GHz

We propose a Low Noise Amplifier (LNA) architecture for power scalable receiver front end (FE) for Zigbee. The motivation for power scalable receiver is to enable minimum power operation while meeting the run-time performance needed. We use simple models to find empirical relations between the available signal and interference levels to come up with required Noise Figure (NF) and 3rd order Intermodulation Product (IIP3) numbers. The architecture has two independent digital knobs to control the NF and IIP3. Acceptable input match while using adaptation has been achieved by using an Active Inductor configuration for the source degeneration inductor of the LNA. The low IF receiver front end (LNA with I and Q mixers) was fabricated in 130nm RFCMOS process and tested.

A hybrid nine-level inverter for IM drive

This paper proposes a new hybrid nine-level inverter topology for IM drive. The nine-level structure is realized by using two three-phase two-level inverters fed by isolated DC voltage sources and six H-bridges fed by capacitors. The number of switches required in this topology is only 36 where as the conventional nine-level topologies require 48 switches. The voltages across the capacitors, feeding the H-bridges that operate at asymmetric voltages, are effectively balanced by making use of the switching state redundancies. In this topology, the requirement of DC link voltage is only half of the maximum magnitude of the voltage space vector. As the two-level inverters are powered by isolated voltage sources, the circulation of triplen harmonic current in the motor winding is prevented. The proposed drive system is capable of functioning in three-level mode in case of any switch failure in H-bridges. The performance of the proposed topology in the entire modulation range is verified by simulation study and experiment.

A Novel VSI- and CSI-Fed Active-Reactive Induction Motor Drive with Sinusoidal Voltages and Currents

Till date load-commutated inverter (LCI)-fed synchronous motor drive configuration is popular in high power applications (>10 MW). The leading power factor operation of synchronous motor by excitation control offers this simple and rugged drive structure. On the contrary, LCI-fed induction motor drive is absent as it always draws lagging power factor current. Therefore, complicated commutation circuit is required to switch off thyristors for a current source inverter (CSI)-driven induction motor. It poses the major hindrance to scale up the power rating of CSI-fed induction motor drive. Anew power topology for LCI-fed induction motor drive for medium-voltage drive application is proposed. A new induction machine (active-reactive induction machine) with two sets of three-phase winding is introduced as a drive motor. The proposed power configuration ensures sinusoidal voltage and current at the motor terminals. The total drive power is shared among a thyristor-based LCI, an insulated gate bipolar transistor (IGBT)-based two-level voltage source inverter (VSI), and a three-level VSI. The benefits of SCRs and IGBTs are explored in the proposed drive. Experimental results from a prototype drive verify the basic concepts of the drive.