Quaternary unary operators

Unary operators are functions of a single variable. Realization of quaternary unary operators (QUOs) using quaternary multiplexer (QMUX) is presented in this paper. QUOs are divided into eight groups on the basis of the number of change overs in the output for an input sequence of 0, 1, 2, 3. This grouping reduces the hardware required to realize them. QMUX with two, three, and four input lines are proposed for the realization of QUOs belonging to the eight groups. A systematic procedure for the selection of QMUX and the implementation of the QUOs are given. The QMUXs are designed using CMOS ICs. The hardware required for their implementation is also discussed.

Case study of a microcomputer-minicomputer link

A microcomputer-minicomputer link, useful in the implementation of network configurations involving microcomputers and minicomputers, is described. The link, between a PDP-11 minicomputer and an 8080 microcomputer is over a serial line between the DZ11 module of the minicomputer and the UART interface of the microcomputer. The details of the essential hardware and software aspects of the link are presented.

A microprocessor-controlled programmable pulse generator

The hardware and the software details of a user-friendly, simple, flexible and inexpensive pulse programmer using programmable counters interfaced to a microprocessor are described. The control of the various parameters that are required for NMR applications is implemented using the microprocessor. The basic hardware is extendable to other applications which require programmable pulse trains.

An interactive graphics system for 2-D drawing and design

This paper is about a software system, GRASS-Graphic Software System for 2-D drawing and design—which has been implemented on a PDP-11/35 system with RSX-11M operating system. It is a low cost interactive graphics system for the design of two dimensional drawings and uses a minimum of hardware. It provides comprehensive facilities for creating, editing, storing and retrieving pictures. It has been implemented in the language Pascal and has the potential to be used as a powerful data-imputting tool for a design-automation system. The important features of the system are its low cost, software character generation and a user-trainable character recognizer, which has been included.

Synergistic Execution of Stream Programs on Multicores with Accelerators

The StreamIt programming model has been proposed to exploit parallelism in streaming applications oil general purpose multicore architectures. The StreamIt graphs describe task, data and pipeline parallelism which can be exploited on accelerators such as Graphics Processing Units (GPUs) or CellBE which support abundant parallelism in hardware. In this paper, we describe a novel method to orchestrate the execution of if StreamIt program oil a multicore platform equipped with an accelerator. The proposed approach identifies, using profiling, the relative benefits of executing a task oil the superscalar CPU cores and the accelerator. We formulate the problem of partitioning the work between the CPU cores and the GPU, taking into account the latencies for data transfers and the required buffer layout transformations associated with the partitioning, as all integrated Integer Linear Program (ILP) which can then be solved by an ILP solver. We also propose an efficient heuristic algorithm for the work-partitioning between the CPU and the GPU, which provides solutions which are within 9.05% of the optimal solution on an average across the benchmark Suite. The partitioned tasks are then software pipelined to execute oil the multiple CPU cores and the Streaming Multiprocessors (SMs) of the GPU. The software pipelining algorithm orchestrates the execution between CPU cores and the GPU by emitting the code for the CPU and the GPU, and the code for the required data transfers. Our experiments on a platform with 8 CPU cores and a GeForce 8800 GTS 512 GPU show a geometric mean speedup of 6.94X with it maximum of 51.96X over it single threaded CPU execution across the StreamIt benchmarks. This is a 18.9% improvement over it partitioning strategy that maps only the filters that cannot be executed oil the GPU - the filters with state that is persistent across firings - onto the CPU.

Pipeline Analog To Ternary Converter

The paper describes the application of the pipelining principle to the realization of an analogue-to-ternary converter. The circuit shows a considerable saving in hard-ware compared with an earlier proposed circuit. The main hardware components used are analogue comparators, subtractors and the delay elements; hence this method of A/T conversion can operate at a higher sampling frequency.

Non-Destructive Method to Estimate the Moisture Content in Bread using Multi-Channel Electrical Impedance Spectroscopy

Bread undergoes several physicochemical changes during storage that results in a rapid loss of freshness. These changes depend on moisture content present in bread product. An instrument based on electrical impedance spectroscopy technique is developed to estimate moisture content of bread at different zones using designed multi-channel ring electrodes. A dedicated AT89S52 microcontroller and associated peripherals are employed for hardware. A constant current is applied across bread loaf through central pair of electrodes and developed potential across different zones of bread loaf are measured using remaining four ring electrode pairs. These measured values of voltage and current are used to measure the impedance at each zone. Electrical impedance behavior of the bread loaf at crust and crumb is investigated during storage. A linear relationship is observed between the measured impedance and moisture content present in crust and crumb of bread loaf during storage of 120 hours.

A Microprocessor-Based Scheme for Testing Protective Relays

This paper presents a general hardware scheme for testing protective relays using microprocessor based systems. The microprocessor simulates the relaying signals for test purpose and monitors the relay performance. Based on the proposed hardware, a teat procedure for directional overcurrent relays is presented in detail. Typical test results of various routine tests conducted on a commercial single phase directional over-current relay clearly demonstrate the efficacy of the proposed technique for conducting tests on commercial relays.

Hybrid Simulation of Queuing-System Dynamics

This paper presents a simple hybrid computer technique to study the transient behaviour of queueing systems. This method is superior to stand-alone analog or digital solution because the hardware requirement is excessive for analog technique whereas computation time is appreciable in the latter case. By using a hybrid computer one can share the analog hardware thus requiring fewer integrators. The digital processor can store the values, play them back at required time instants and change the coefficients of differential equations. By speeding up the integration on the analog computer it is feasible to solve a large number of these equations very fast. Hybrid simulation is even superior to the analytic technique because in the latter case it is difficult to solve time-varying differential equations.

Experimental networking of microcomputers and a minicomputer

The objective of this paper is to discuss some hardware and software features of an experimental network of 8080 and 8085 microcomputers named Micronet. The interprocessor communication in the ring network is established using ring interfaces consisting of universal synchronous-asynchronous receivers-transmitters (USARTs). Another aspect considered is the interfacing of an 8080 microcomputer to a PDP-11/35 minicomputer and the development of the software for the microcomputer-minicomputer link which has been established over a serial line using the USART interface of the microcomputer and the DZ11 module of the minicomputer. This is useful in developing a host-satellite configuration of microcomputers and the minicomputer.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

An Input Triggered Polymorphic ASIC for H.264 Decoding

This paper reports the design of an input-triggered polymorphic ASIC for H.264 baseline decoder. Hardware polymorphism is achieved by selectively reusing hardware resources at system and module level. Complete design is done using ESL design tools following a methodology that maintains consistency in testing and verification throughout the design flow. The proposed design can support frame sizes from QCIF to 1080p.

A Petri net model for evaluating packet buffering strategies in a network processor

Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri net model of IP forwarding application on IXP2400 that models the different levels of the memory hierarchy. The cell based interface used to receive and transmit packets in a network processor leads to some small size DRAM accesses. Such narrow accesses to the DRAM expose the bank access latency, reducing the bandwidth that can be realized. With real traces up to 30% of the accesses are smaller than the cell size, resulting in 7.7% reduction in DRAM bandwidth. To overcome this problem, we propose buffering these small chunks of data in the on chip scratchpad memory. This scheme also exploits greater degree of parallelism between different levels of the memory hierarchy. Using real traces from the internet, we show that the transmit rate can be improved by an average of 21% over the base scheme without the use of additional hardware. Further, the impact of different traffic patterns on the network processor resources is studied. Under real traffic conditions, we show that the data bus which connects the off-chip packet buffer to the micro-engines, is the obstacle in achieving higher throughput.

COMPASS – A tool for evaluation of compression strategies for embedded processors

A major concern of embedded system architects is the design for low power. We address one aspect of the problem in this paper, namely the effect of executable code compression. There are two benefits of code compression – firstly, a reduction in the memory footprint of embedded software, and secondly, potential reduction in memory bus traffic and power consumption. Since decompression has to be performed at run time it is achieved by hardware. We describe a tool called COMPASS which can evaluate a range of strategies for any given set of benchmarks and display compression ratios. Also, given an execution trace, it can compute the effect on bus toggles, and cache misses for a range of compression strategies. The tool is interactive and allows the user to vary a set of parameters, and observe their effect on performance. We describe an implementation of the tool and demonstrate its effectiveness. To the best of our knowledge this is the first tool proposed for such a purpose.

Compiler-assisted instruction decoder energy optimization for clustered VLIW architectures

Traditionally, an instruction decoder is designed as a monolithic structure that inhibit the leakage energy optimization. In this paper, we consider a split instruction decoder that enable the leakage energy optimization. We also propose a compiler scheduling algorithm that exploits instruction slack to increase the simultaneous active and idle duration in instruction decoder. The proposed compiler-assisted scheme obtains a further 14.5% reduction of energy consumption of instruction decoder over a hardware-only scheme for a VLIW architecture. The benefits are 17.3% and 18.7% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively.