An Input Triggered Polymorphic ASIC for H.264 Decoding
| Data(s) |
2009
|
|---|---|
| Resumo |
This paper reports the design of an input-triggered polymorphic ASIC for H.264 baseline decoder. Hardware polymorphism is achieved by selectively reusing hardware resources at system and module level. Complete design is done using ESL design tools following a methodology that maintains consistency in testing and verification throughout the design flow. The proposed design can support frame sizes from QCIF to 1080p. |
| Formato |
application/pdf |
| Identificador |
http://eprints.iisc.ernet.in/25071/1/asic.pdf Rao, Adarsha and Alle, Mythri and Sainath, V and Shaik, Reyaz and Chowhan, Rajashekhar and Sankaraiah, S and Mantha, Sravanthi and Nandy, SK and Narayan, Ranjani (2009) An Input Triggered Polymorphic ASIC for H.264 Decoding. In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 07-09, 2009, Boston, MA, USA, pp. 106-113. |
| Publicador |
IEEE |
| Relação |
http://www.computer.org/portal/web/csdl/doi/10.1109/ASAP.2009.7 http://eprints.iisc.ernet.in/25071/ |
| Palavras-Chave | #Supercomputer Education & Research Centre |
| Tipo |
Conference Paper PeerReviewed |
