Use of adult male bonnet monkeys (Macaca radiata) for testing the biological activity of gonadotropin releasing hormone and its analogues

The effect of injecting agonistic and antagonistic analogues of gonadotropin releasing hormone analogues on serum testosterone levels was checked in adult and immature male bonnet monkeys. Of the agonistic analogues Buserelin, Ovurelin and D-Phe6 Gln8 GnRH were found to be most potent in increasing serum testosterone levels in the adult male bonnet monkeys. While 27-month-old monkeys responded well to des Gly10 GnRH, only marginal response was observed in the case of 15-month-old monkeys. Studies carried out with Ovurelin indicated that it was not effective in causing desensitization in adult monkeys. The antagonistic analogue was effective in blocking nocturnal surge of serum testosterone. Based on these studies it is suggested the adult male bonnet monkeys can be effectively used for testing the activity of GnRH analogues.

Testing the efficacy of a chilli-tobacco rope fence as a deterrent against crop-raiding elephants

Chilli-based repellents have shown promise as deterrents against crop-raiding elephants in Africa. We experimented with ropes coated with chilli-based repellent as a cheap alternative to existing elephant cropraid deterrent methods in India. Three locations (Buxa Tiger Reserve, Wyanad Wildlife Sanctuary and Hosur Forest Division) representing varying rainfall regimes from high to low, and with histories of intense elephant-agriculture conflict, were selected for the experiments that were conducted over 2-3 months during the pre-harvest period of the kharif season in late 2006. Chilli and tobacco powder mixed with waste oil was applied to ropes strung around agricultural fields of 1.4-5.5 km perimeter and elephant approaches were monitored. Elephants breached the rope fences a few times at all three study sites. Female-led herds were far more deterred (practically 100% reduction) than were solitary males (c. 50%) by the chilli-tobacco rope. Efficacy of this method as a deterrent was significantly better in the low-rainfall regime relative to medium and high-rainfall regimes. The initial promising results present a case for more rigorous experimentation; these would help determine if the elephants avoiding the rope are responding physiologically to the chilli-tobacco smell or merely reacting cautiously to a novel substance in their environment.

Compiler-assisted power optimization for clustered VLIW architectures

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file. We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine. (C) 2010 Elsevier B.V. All rights reserved.

Analyzing Cache Performance Bottlenecks of STM Applications and addressing them with Compiler's help

Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs as an alternative to traditional lock based synchronization. However adoption of STM in mainstream software has been quite low due to its considerable overheads and its poor cache/memory performance. In this paper, we perform a detailed study of the cache behavior of STM applications and quantify the impact of different STM factors on the cache misses experienced by the applications. Based on our analysis, we propose a compiler driven Lock-Data Colocation (LDC), targeted at reducing the cache overheads on STM. We show that LDC is effective in improving the cache behavior of STM applications by reducing the dcache miss latency and improving execution time performance.

Microtensile testing of a free-standing Pt-aluminide bond coat

A finite element method (FEM)-based study has been carried out for the design of flat microtensile samples to evaluate tensile properties of Pt-aluminide (PtAl) bond coats. The critical dimensions of the sample have been determined using a two-dimensional elastic stress analysis. In the present testing scheme, the ratio of the dimensions of the holding length to the fillet radius of the sample was found important to achieve failure within the gage length. The effect of gage length and grip head length also has been examined. The simulation predictions have been experimentally verified by conducting microtensile test of an actual PtAl bond coat at room temperature. The sample design and testing scheme suggested in this study have also been found suitable for evaluation of tensile properties at high temperature. (C) 2010 Elsevier Ltd. All rights reserved.

Influence of anvil supports and overhangs in dynamic analysis of three point bend testing

Optimum design of dynamic fracture test rigs demands a thorough appreciation of beam vibration under impact. Analyses invariably presume rigid anvils, and neglect overhang effects. The beam response predicted analytically and numerically in this paper highlights the significant role of anvil rigidity and beam overhangs on the impact dynamics of three point bend (3PB) specimens.

A Flat Concurrent Prolog compiler for PARAM

We describe a compiler for the Flat Concurrent Prolog language on a message passing multiprocessor architecture. This compiler permits symbolic and declarative programming in the syntax of Guarded Horn Rules, The implementation has been verified and tested on the 64-node PARAM parallel computer developed by C-DAC (Centre for the Development of Advanced Computing, India), Flat Concurrent Prolog (FCP) is a logic programming language designed for concurrent programming and parallel execution, It is a process oriented language, which embodies dataflow synchronization and guarded-command as its basic control mechanisms. An identical algorithm is executed on every processor in the network, We assume regular network topologies like mesh, ring, etc, Each node has a local memory, The algorithm comprises of two important parts: reduction and communication, The most difficult task is to integrate the solutions of problems that arise in the implementation in a coherent and efficient manner. We have tested the efficacy of the compiler on various benchmark problems of the ICOT project that have been reported in the recent book by Evan Tick, These problems include Quicksort, 8-queens, and Prime Number Generation, The results of the preliminary tests are favourable, We are currently examining issues like indexing and load balancing to further optimize our compiler.

Counselling and predictive testing for familial adenomatous polyposis in a rural South Indian community

Background—Mutations of the APC gene cause familial adenomatous polyposis (FAP), a hereditary colorectal cancer predisposition syndrome.Aims—To conduct a cost comparison analysis of predictive genetic testing versus conventional clinical screening for individuals at risk of inheriting FAP, using the perspective of a third party payer. Methods—All direct health care costs for both screening strategies were measured according to time and motion, and the expected costs evaluated using a decision analysis model.Results—The baseline analysis predicted that screening a prototype FAP family would cost $4975/£3109 by molecular testingand $8031/£5019 by clinical screening strategy, when family members were monitored with the same frequency of clinical surveillance (every two to three years). Sensitivity analyses revealed that the genetic testing approach is cost saving for key variables including the kindred size, the age of screening onset, and the cost of mutation identification in a proband. However, if the APC mutation carriers were monitored at an increased (annual) frequency, the cost of the genetic screening strategy increased to $7483/ £4677 and was especially sensitive to variability in age of onset of screening, family size, and cost of genetic testing of at risk relatives. Conclusions—In FAP kindreds, a predictive genetic testing strategy costs less than conventional clinical screening, provided that the frequency of surveillance is identical using either strategy. An additional significant benefit is the elimination of unnecessary colonic examinations for those family members found to be noncarriers.

Rapid method of consolidation testing

The determination of consolidation characteristics forms an important aspect in the design of foundations and other earth-retaining structures. The conventional consolidation test as originally proposed by Teaaghi takes considerable time (more than 15 days in highly compressible soils with low coefficient of consolidation) and effort. Any effort to reduce the duration of testing will be desirable from several considerations. In this paper, an attempt has been made to propose a rapid method of consolidation testing. In the proposed method, the next load increment is applied as soon as the necessary time required to identify the percent consolidation is reached and to evaluate the coefficient of consolidation by one of the popular curve-fitting procedures. The rectangular hyperbola method has been used to identify the percent consolidation reached after any load increment, and to determine the coefficient of consolidation, before making the next load increment. The time required to complete the test using the rapid consolidation method could be as low as 4-5 h compared with 1 or 2 weeks in the case of the conventional consolidation test.

Dynamic path profile aided recompilation in a JAVA just-in-time compiler

Just-in-Time (JIT) compilers for Java can be augmented by making use of runtime profile information to produce better quality code and hence achieve higher performance. In a JIT compilation environment, the profile information obtained can be readily exploited in the same run to aid recompilation and optimization of frequently executed (hot) methods. This paper discusses a low overhead path profiling scheme for dynamically profiling AT produced native code. The profile information is used in recompilation during a subsequent invocation of the hot method. During recompilation tree regions along the hot paths are enlarged and instruction scheduling at the superblock level is performed. We have used the open source LaTTe AT compiler framework for our implementation. Our results on a SPARC platform for SPEC JVM98 benchmarks indicate that (i) there is a significant reduction in the number of tree regions along the hot paths, and (ii) profile aided recompilation in LaTTe achieves performance comparable to that of adaptive LaTTe in spite of retranslation and profiling overheads.

Study of Brittle-to-ductile-transition in Pt-aluminide bond coat using micro-tensile testing method

The Brittle-to-ductile-transition-temperature (BDTT) of free-standing Pt-aluminide (PtAl) coating specimens, i.e. stand-alone coating specimens without any substrate, was determined by micro-tensile testing technique. The effect of Pt content, expressed in terms of the thickness of initial electro-deposited Pt layer, on the BDTT of the coating has been evaluated and an empirical correlation drawn. Increase in the electrodeposited Pt layer thickness from nil to 10 mu m was found to cause an increase in the BDTT of the coating by about 100 degrees C.

Compiler-Directed Frequency and Voltage Scaling for a Multiple Clock Domain

Multiple Clock Domain processors provide an attractive solution to the increasingly challenging problems of clock distribution and power dissipation. They allow their chips to be partitioned into different clock domains, and each domain’s frequency (voltage) to be independently configured. This flexibility adds new dimensions to the Dynamic Voltage and Frequency Scaling problem, while providing better scope for saving energy and meeting performance demands. In this paper, we propose a compiler directed approach for MCD-DVFS. We build a formal petri net based program performance model, parameterized by settings of microarchitectural components and resource configurations, and integrate it with our compiler passes for frequency selection.Our model estimates the performance impact of a frequency setting, unlike the existing best techniques which rely on weaker indicators of domain performance such as queue occupancies(used by online methods) and slack manifestation for a particular frequency setting (software based methods).We evaluate our method with subsets of SPECFP2000,Mediabench and Mibench benchmarks. Our mean energy savings is 60.39% (versus 33.91% of the best software technique)in a memory constrained system for cache miss dominated benchmarks, and we meet the performance demands.Our ED2 improves by 22.11% (versus 18.34%) for other benchmarks. For a CPU with restricted frequency settings, our energy consumption is within 4.69% of the optimal.