Photoimpedance characterization of polymer field-effect transistor

The small signal ac response is measured across the source-drain terminals of poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene) field-effect transistor under dc bias to obtain the equivalent circuit parameters in the dark, and under a monochromatic light (540 nm) of various intensities. The numerically simulated response based on these parameters shows deviation at low frequency which is related to the charge accumulation at the interface and the contact resistance at the electrodes. This method can be used to differentiate the photophysical phenomena occurring in the bulk from that at the metal-semiconductor interface for polymer field-effect transistors. ©2009 American Institute of Physics

Ultralow noise field-effect transistor from multilayer graphene

We present low-frequency electrical resistance fluctuations, or noise, in graphene-based field-effect devices with varying number of layers. In single-layer devices, the noise magnitude decreases with increasing carrier density, which behaved oppositely in the devices with two or larger number of layers accompanied by a suppression in noise magnitude by more than two orders in the latter case. This behavior can be explained from the influence of external electric field on graphene band structure, and provides a simple transport-based route to isolate single-layer graphene devices from those with multiple layers. ©2009 American Institute of Physics

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor

In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long channel cylindrical body structure. The potential distribution at each and every point of the of the wire is derived with a closed form solution of two dimensional Poisson's equation, which is then used to model the threshold voltage. Proposed model can be treated as a generalized model, which is valid for both surround gate and semi-surround gate cylindrical transistors. The accuracy of proposed model is verified for different device geometry against the results obtained from three dimensional numerical device simulators and close agreement is observed.

Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification or Cur is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit fly some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

Intrinsic limits of subthreshold slope in biased bilayer graphene transistor

In this work, we investigate the intrinsic limits of subthreshold slope in a dual gated bilayer graphene transistor using a coupled self-consistent Poisson-bandstructure solver. We benchmark the solver by matching the bias dependent band gap results obtained from the solver against published experimental data. We show that the intrinsic bias dependence of the electronic structure and the self-consistent electrostatics limit the subthreshold slope obtained in such a transistor well above the Boltzmann limit of 60 mV/decade at room temperature, but much below the results experimentally shown till date, indicating room for technological improvement of bilayer graphene.

Asymmetric cross-coupled differential pair configuration to realize neuron activation function and its derivative

In this brief, we present a new circuit technique to generate the sigmoid neuron activation function (NAF) and its derivative (DNAF). The circuit makes use of transistor asymmetry in cross-coupled differential pair to obtain the derivative. The asymmetry is introduced through external control signal, as and when required. This results in the efficient utilization of the hard-ware by realizing NAF and DNAF using the same building blocks. The operation of the circuit is presented in the subthreshold region for ultra low-power applications. The proposed circuit has been experimentally prototyped and characterized as a proof of concept on the 1.5-mum AMI technology.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

Probing top-gated field effect transistor of reduced graphene oxide monolayer made by dielectrophoresis

We demonstrate a top-gated field effect transistor made of a reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. The Raman spectrum of RGO flakes of typical size of 5 mu m x 5 mu m shows a single 2D band at 2687 cm(-1), characteristic of single-layer graphene.The two-probe current-voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 mu m using ac dielectrophoresis, show ohmic behavior with a resistance of similar to 37 k Omega. The temperature dependence of the resistance (R) of RGO measured between 305 K and 393 K yields a temperature coefficient of resistance [dR/dT]/R similar to -9.5 x 10(-4)/K, the same as that of mechanically exfoliated single-layer graphene. The field-effect transistor action was obtained by electrochemical top-gating using a solid polymer electrolyte (PEO + LiClO4) and Pt wire. The ambipolar nature of graphene flakes is observed up to a doping level of similar to 6 x 10(12)/cm(2) and carrier mobility of similar to 50 cm(2)/V s. The source-drain current characteristics show a tendency of current saturation at high source-drain voltage which is analyzed quantitatively by a diffusive transport model. (C) 2010 Elsevier Ltd. All rights reserved.

Al/SiC carriers for microwave integrated circuits by a new technique of pressureless infiltration

Materials with high thermal conductivity and thermal expansion coefficient matching with that of Si or GaAs are being used for packaging high density microcircuits due to their ability of faster heat dissipation. Al/SiC is gaining wide acceptance as electronic packaging material due to the fact that its thermal expansion coefficient can be tailored to match with that of Si or GaAs by varying the Al:SiC ratio while maintaining the thermal conductivity more or less the same. In the present work, Al/SiC microwave integrated circuit (MIC) carriers have been fabricated by pressureless infiltration of Al-alloy into porous SiC preforms in air. This new technique provides a cheaper alternative to pressure infiltration or pressureless infiltration in nitrogen in producing Al/SiC composites for electronic packaging applications. Al-alloy/65vol% SiC composite exhibited a coefficient of thermal expansion of 7 x 10(-6) K-1 (25 degrees C-100 degrees C) and a thermal conductivity of 147 Wm(-1) K-1 at 30 degrees C. The hysteresis observed in thermal expansion coefficient of the composite in the temperature range 100 degrees C-400 degrees C has been attributed to the presence of thermal residual stresses in the composite. Thermal diffusivity of the composite measured over the temperature range from 30 degrees C to 400 degrees C showed a 55% decrease in thermal diffusivity with temperature. Such a large decrease in thermal diffusivity with temperature could be due to the presence of micropores, microcracks, and decohesion of the Al/SiC interfaces in the microstructure (all formed during cooling from the processing temperature). The carrier showed satisfactory performance after integrating it into a MIC.

Research note A novel BIMOS Schmitt trigger

A new Schmitt trigger circuit based on the lambda bipolar transistor is presented. This circuit which exhibits a hysteresis in its transfer characteristic seems to use a smaller chip area than many of the circuits proposed so far.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

Interfaces and traps in pentacene field-effect transistor

The equivalent circuit parameters for a pentacene organic field-effect transistor are determined from low frequency impedance measurements in the dark as well as under light illumination. The source-drain channel impedance parameters are obtained from Bode plot analysis and the deviations at low frequency are mainly due to the contact impedance. The charge accumulation at organic semiconductor-metal interface and dielectric-semiconductor interface is monitored from the response to light as an additional parameter to find out the contributions arising from photovoltaic and photoconductive effects. The shift in threshold voltage is due to the accumulation of photogenerated carriers under source-drain electrodes and at dielectric-semiconductor interface, and also this dominates the carrier transport. The charge carrier trapping at various interfaces and in the semiconductor is estimated from the dc and ac impedance measurements under illumination. (c) 2010 American Institute of Physics. doi: 10.1063/1.3517085]

Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor

In this paper, a physically based analytical quantum linear threshold voltage model for short channel quad gate MOSFETs is developed. The proposed model, which is suitable for circuit simulation, is based on the analytical solution of 3-D Poisson and 2-D Schrodinger equation. Proposed model is fully validated against the professional numerical device simulator for a wide range of device geometries and also used to analyze the effect of geometry variation on the threshold voltage.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well