RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

Parallel min-cut placement on reduced hardware SIMD architecture.

Massively parallel SIMD computing is applied to obtain an order of magnitude improvement in the executional speed of an important algorithm in VLSI design automation. The physical design of a VLSI circuit involves logic module placement as a subtask. The paper is concerned with accelerating the well known Min-cut placement technique for logic cell placement. The inherent parallelism of the Min-cut algorithm is identified, and it is shown that a parallel machine based on the efficient execution of the placement procedure.

A fault-tolerant multi-transputer architecture

A new fault-tolerant multi-transputer architecture capable of tolerating failure of any one component in the system is described. In the proposed architecture the processing nodes are automatically reconfigured in the event of a fault and the computations continue from the stage where the fault occurred. The process of reconfiguration is transparent to the user, and the identity of the failed component is communicated to the user along with the results of computations. Parallel solution of a typical engineering problem involving solution of Laplace's equation by the boundary element method has been implemented. The performance of the architecture in the event of faults has been investigated.

Architecture of Physalis Mottle Tymovirus as Probed by Monoclonal Antibodies and Cross-Linking Studies

Physalis mottle tymovirus (previously named belladonna mottle virus, Iowa strain) RNA was cross-linked to its coat protein by exposure of the intact virus to ultraviolet light. The site of cross-linking of the coat protein with the RNA was identified as Lys-10 by sequencing the oligonucleotide-linked tryptic peptide obtained upon HPLC separation subsequent to enzymetic digestion of the cross-linked and dissociated virus. Three monoclonal antibodies PA3B2, PB5G9, and PF12C9, obtained using denatured coat protein as antigen, cross-reacted effectively with the intact virus indicating that the epitopes recognized by these monoclonals are on the surface of the virus. Using the peptides generated by digestion with CNBr, clostripain, V-8 protease, or trypsin and a recombinant protein lacking the N-terminal 21 residues expressed from a cDNA clone, it was shown that PA3B2 recognizes the sequence 22-36 on the coat protein while PB5G9 and PF12C9 recognize region 75-110. These results suggest that Lys-10 is one of the specific sites through which the RNA interacts in the intact virus. The polypeptide segment (region 22-36) following this buried portion as well as the epitope within the region 75-110 are exposed in the intact virus. These observations are consistent with the canonical β-barrel structure observed in certain other plant viruses.

Area Optimized H.264 Intra Prediction Architecture for 1080p HD Resolution

High performance video standards use prediction techniques to achieve high picture quality at low bit rates. The type of prediction decides the bit rates and the image quality. Intra Prediction achieves high video quality with significant reduction in bit rate. This paper present an area optimized architecture for Intra prediction, for H.264 decoding at HDTV resolution with a target of achieving 60 fps. The architecture was validated on Virtex-5 FPGA based platform. The architecture achieves a frame rate of 64 fps. The architecture is based on multi-level memory hierarchy to reduce latency and ensure optimum resources utilization. It removes redundancy by reusing same functional blocks across different modes. The proposed architecture uses only 13% of the total LUTs available on the Xilinx FPGA XC5VLX50T.

Diacetylenic lipid tubules:experimental evidence for a chiral molecular architecture

Molecular self-assembly is of key importance for the rational design of advanced materials. To investigate the causal relation between molecular structure and the consequent self-assembled microstructure, self-assembled tubules of diacetylenic lipids were studied. Circular-dichroism studies give experimental evidence that the formation of tubules is driven by chiral molecular packing, in agreement with recent theories of tubules. On the basis of these results, a molecular mechanism for the formation of tubules is proposed.

Primary structure of sesbania mosaic virus coat protein: its implications to the assembly and architecture of the virus

Sesbania mosaic virus (SMV) is a plant virus that infects Sesbania grandiflora plants in Andhra Pradesh, India. The amino acid sequence of the coat protein of SMV was determined using purified peptides generated by cleavage with trypsin, chymotrypsin, V8 protease and clostripain. The 230 residues so far determined were compared to the corresponding residues of southern bean mosaic virus (SBMV), the type member of sobemoviruses. The overall identity between the sequences is 61.7%. The amino terminal 64 residues, which constitute an independent domain (R-domain) known to interact with RNA, are conserved to a lower extent (52.5%). Comparison of the positively charged residues in this domain suggests that the RNA-protein interactions are considerably weaker in SMV. The residues that constitute the major domain of the coat protein, the surface domain (S-domain, residues 65-260), are better conserved (66.5%). The positively charged residues of this domain that face the nucleic acid are well conserved. The longest conserved stretch of residues (131-142) corresponds to the loop involved in intersubunit interactions between subunits related by the quasi 3-fold symmetry. A unique cation binding site located on the quasi 3-fold axis contributes to the stability of SMV. These differences are reflected in the increased stability of the SMV coat protein and its ability to be reconstituted with RNA at pH 7.5. A major epitope was identified using monoclonal antibodies to SMV in the segment 201-223 which contains an exposed helix in the capsid structure. This region is highly conserved between SMV and SBMV (70%) suggesting that it could represent the site of an important function such as vector recognition.