Analysis of integrated optofluidic lab-on-a-chip fluorescence biosensor based on transmittance of light through a fluidic gap

Sensitivity analysis is an important aspect to be looked into while designing lab-on-a-chip systems. In this paper we will be showing with appropriate design that the best sensitivity of the fluorescence biosensor is achieved for an optimal width of fluidic gap, corresponding to a particular mode spot size. We will be also showing that the sensitivity of the biosensor is affected by efficiency of light coupling, which is influenced by changes in the width of fluidic gap, refractive index of the fluid and higher order modes.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Microstructure and compression behavior of chip consolidated magnesium

Chips produced by turning a commercial purity magnesium billet were cold compacted and then hot extruded at four different temperatures: 250, 300, 350, and 400 degrees C. Cast billets, of identical composition, were also extruded as reference material. Chip boundaries, visible even after 49: 1 extrusion at 400 degrees C, were observed to suppress grain coarsening. Although 250 degrees C extruded chip-consolidated product showed early onset of yielding and lower ductility, fully dense material (extruded at 400 degrees C) had nearly 40% reduction in grain size with 22% higher yield strength and comparable ductility as that of the reference. The study highlights the role of densification and grain refinement on the compression behavior of chip consolidated specimens.

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Adaptive power optimization of on-chip SNUCA cache on tiled chip multicore architecture using remap policy

Advances in technology have increased the number of cores and size of caches present on chip multicore platforms(CMPs). As a result, leakage power consumption of on-chip caches has already become a major power consuming component of the memory subsystem. We propose to reduce leakage power consumption in static nonuniform cache architecture(SNUCA) on a tiled CMP by dynamically varying the number of cache slices used and switching off unused cache slices. A cache slice in a tile includes all cache banks present in that tile. Switched-off cache slices are remapped considering the communication costs to reduce cache usage with minimal impact on execution time. This saves leakage power consumption in switched-off L2 cache slices. On an average, there map policy achieves 41% and 49% higher EDP savings compared to static and dynamic NUCA (DNUCA) cache policies on a scalable tiled CMP, respectively.

Sensitivity analysis based on mode mismatch for an optofluidic lab on a chip biosensor

In this paper we will be presenting the effect of fluidic gap, the effect of change of refractive index of the fluid contained in the gap, and the effect of higher order modes on the efficiency of light coupling and thus on the on the sensitivity of the sensor.

Sensitivity analysis based on Mode Mismatch for an optofluidic lab on a chip biosensor

In this paper we will be presenting the effect of fluidic gap, the effect of change of refractive index of the fluid contained in the gap, and the effect of higher order modes on the efficiency of light coupling and thus on the on the sensitivity of the sensor.

Analysis of integrated optofluidic lab-on-a-chip sensor based on refractive index and absorbance sensing

The analysis of a fully integrated optofluidic lab-on-a-chip sensor is presented in this paper. This device is comprised of collinear input and output waveguides that are separated by a microfluidic channel. When light is passed through the analyte contained in the fluidic gap, optical power loss occurs owing to absorption of light. Apart from absorption, a mode-mismatch between the input and output waveguides occurs when the light propagates through the fluidic gap. The degree of mode-mismatch and quantum of optical power loss due to absorption of light by the fluid form the basis of our analysis. This sensor can detect changes in refractive index and changes in concentration of species contained in the analyte. The sensitivity to detect minute changes depends on many parameters. The parameters that influence the sensitivity of the sensor are mode spot size, refractive index of the fluid, molar concentration of the species contained in the analyte, width of the fluidic gap, and waveguide geometry. By correlating various parameters, an optimal fluidic gap distance corresponding to a particular mode spot size that achieves the best sensitivity is determined both for refractive index and absorbance-based sensing.

Efficient Cache Exploration Method for a Tiled Chip Multiprocessor

Past studies use deterministic models to evaluate optimal cache configuration or to explore its design space. However, with the increasing number of components present on a chip multiprocessor (CMP), deterministic approaches do not scale well. Hence, we apply probabilistic genetic algorithms (GA) to determine a near-optimal cache configuration for a sixteen tiled CMP. We propose and implement a faster trace based approach to estimate fitness of a chromosome. It shows up-to 218x simulation speedup over the cycle-accurate architectural simulation. Our methodology can be applied to solve other cache optimization problems such as design space exploration of cache and its partitioning among applications/ virtual machines.

Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors

It is essential to accurately estimate the working set size (WSS) of an application for various optimizations such as to partition cache among virtual machines or reduce leakage power dissipated in an over-allocated cache by switching it OFF. However, the state-of-the-art heuristics such as average memory access latency (AMAL) or cache miss ratio (CMR) are poorly correlated to the WSS of an application due to 1) over-sized caches and 2) their dispersed nature. Past studies focus on estimating WSS of an application executing on a uniprocessor platform. Estimating the same for a chip multiprocessor (CMP) with a large dispersed cache is challenging due to the presence of concurrently executing threads/processes. Hence, we propose a scalable, highly accurate method to estimate WSS of an application. We call this method ``tagged WSS (TWSS)'' estimation method. We demonstrate the use of TWSS to switch-OFF the over-allocated cache ways in Static and Dynamic NonUniform Cache Architectures (SNUCA, DNUCA) on a tiled CMP. In our implementation of adaptable way SNUCA and DNUCA caches, decision of altering associativity is taken by each L2 controller. Hence, this approach scales better with the number of cores present on a CMP. It gives overall (geometric mean) 26% and 19% higher energy-delay product savings compared to AMAL and CMR heuristics on SNUCA, respectively.

Simultaneous measurements of thickness and temperature profile of the lubricant film at chip-tool interface during machining process using luminescent sensors

Simultaneous measurements of thickness and temperature profile of the lubricant film at chip-tool interface during machining have been studied in this experimental programme. Conventional techniques such as thermography can only provide temperature measurement under controlled environment in a laboratory and without the addition of lubricant. The present study builds on the capabilities of luminescent sensors in addition to direct image based observations of the chip-tool interface. A suite of experiments conducted using different types of sensors are reported in this paper, especially noteworthy are concomitant measures of thickness and temperature of the lubricant. (C) 2014 Elsevier Ltd.

Design and Validation of On-chip Planar Mixer Based on Advection and Viscoelastic Effects

Mixing at low Reynolds number is usually due to diffusion and requires longer channel lengths for complete mixing. In order to reduce the mixing lengths, advective flow can be induced by varying the channel geometry. Additionally, in non-newtonian fluids, appropriate modifications to channel geometry can be used to aid the mixing process by capitalizing on their viscoelastic nature. Here we have exploited the advection and viscoelastic effects to implement a planar passive micro-mixer. Microfluidic devices incorporating different blend of mixing geometries were conceived. The optimum design was chosen based on the results of the numerical simulations performed in COMSOL. The chosen design had sudden expansion and contraction along with teeth patterns along the channel walls to improve mixing. Mixing of two different dyes was performed to validate the mixing efficiency. Particle dispersion experiments were also carried out. The results indicated effective mixing. In addition, the same design was also found to be compatible with electrical power free pumping mechanism like suction. The proposed design was then used to carry out on-chip chemical cell lysis with human whole blood samples to establish its use with non-newtonian fluids. Complete lysis of the erythrocytes was observed leaving behind the white blood cells at the outlet.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.