A 100MHz to 1GHz, 0.35V to 1.5V supply 256 x 64 SRAM mock using symmetrized 9T SRAM cell with controlled read

In this paper, we present Dynamic Voltage and Frequency Managed 256 x 64 SRAM block in 65nm technology, for frequency ranging from 100MHz to 1GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose Static Noise Margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and Hold Noise Margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag-super-cut-off in stand-by mode without affecting its performance in active mode of operation. The Read Bit Line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

A hybrid computer for X-ray crystallography

A hybrid computer for structure factor calculations in X-ray crystallography is described. The computer can calculate three-dimensional structure factors of up to 24 atoms in a single run and can generate the scatter functions of well over 100 atoms using Vand et al., or Forsyth and Wells approximations. The computer is essentially a digital computer with analog function generators, thus combining to advantage the economic data storage of digital systems and simple computing circuitry of analog systems. The digital part serially selects the data, computes and feeds the arguments into specially developed high precision digital-analog function generators, the outputs of which being d.c. voltages, are further processed by analog circuits and finally the sequential adder, which employs a novel digital voltmeter circuit, converts them back into digital form and accumulates them in a dekatron counter which displays the final result. The computer is also capable of carrying out 1-, 2-, or 3-dimensional Fourier summation, although in this case, the lack of sufficient storage space for the large number of coefficients involved, is a serious limitation at present.

An Improved Compact Compliant Mechanism for an External Pipe-Crawler

An external pipe-crawling device presented in this paper aids the inspection of pipes in hazardous environments and areas inaccessible to humans. The principal component of our design, which uses inchworm type motion, is a compliant ring mechanism actuated using shape memory alloy (SMA) wire. It was fabricated and tested and was reported in our earlier work. But this device had a drawback of low crawling speed (about 1 mm/min) owing to the delay in heating and cooling of the SMA strips in the linear actuation. Additionally, that design also had the difficulties of mounting on pipes with closed ends, large radial span, and the need for housing for electrical insulation and guiding of the SMA wire. In this paper we present a compact design that overcomes the difficulties of the earlier design. In particular, we present a compact compliant mechanism with two halves so as to enable mounting and un-mounting on any closed or open pipe. Another feature is the presence of insulation and guiding of the SMA wire without housing. This design results in a reduction of the radial span of the ring from 22 mm to 12 mm, and the stiffness of the mechanism and the SMA wire are matched. An SMA helical spring is to used in the place of an SMA strip to increase the crawling speed of the device. A microcontroller-based circuitry is also fitted to cyclically.activate the SMA wires and springs.

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read

In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose static noise margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and hold noise margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag- super-cut-off in stand-by mode without affecting its performance in active mode of operation. The read bit line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

Multi-point sensing system for plantar pressure measurement

In this paper, the development of a novel multipoint pressure sensor system suitable for the measurement of human foot pressure distribution has been presented. It essentially consists of a matrix of cantilever sensing elements supported by beams. Foil type strain gauges have been employed for the conversion of foot pressure in to proportional electrical response. Information on the signal conditioning circuitry used is given. Also, the results obtained on the performance of the system are included.

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

Developments in amplitude-comparator techniques for distance relays

The paper reports the development of new amplitude-comparator techniques which allow the instantaneous comparison of the amplitude of the signals derived from primary line quantities. These techniques are used to derive a variety of impedance characteristics. The merits of the new relaying system are: the simple mode of the relay circuitry, the derivation of closed polar characteristics (i.e. quadrilateral) by a single measuring gate and sharp discontinuities in the polar characteristics. Design principles and circuit models in their schematic form are described and, in addition, a comprehensive theoretical basis for comparison is also presented. Dynamic test results are presented for a quadrilateral characteristic of potentially general application.

New possibilities in amplitude- and phase-comparison techniques for distance relays

The paper reports further work on the amplitude-comparison technique described by the same authors in a previous paper. This technique is extended to develop improved polar characteristics. Discontinuous polar characteristics, like directional parallelograms, are obtained by a single measuring gate with a simple mode of relay circuitry, whereas two measuring gates are required to provide a directional-quadrilateral characteristic of potentially general application. The paper also describes some new possibilities in phase-comparison methods for distance-protection schemes. Comparator models which effect the amplitude and phase comparison of the relaying signals are described in their schematic form. A comprehensive theoretical basis for comparison is also presented.

Composite instantaneous comparators basis for design and their transient performance

Principles of design of composite instantaneous comparators (a combination of amplitude- and phase- comparison techniques) are laid out to provide directional, directional-reactance, nonoffset-resistance and conductance characteristices. The respective signals provided by the voltage transformer and the current transformer are directly used as relaying signals without resorting to any form of mixing. Phase shifts required, are obtained by using magnetic ferrite cores in a novel manner. Sampling units employing a combination of ferrite cores and semiconductor devices provide highly reliable designs. Special attention is paid to the choice of relaying signals, to eliminate the need for any synchronisation or modification and to avoid `image¿ characteristics. These factors have resulted in a considerable simplification of the practical circuitry. A thyristor AND circuit is employed in dual comparator units to provide the final tripping, and leads to a circuit which is much less sensitive to extraneous signals than a single-thyristor unit.

Three-system and single-system static distance relays

Static distance relays employing semiconductor devices as their active elements offer many advantages over the conventional electromagnetic and rectifier relays. The paper describes single-system and three-system static distance relays, which depend for their operation on the instantaneous-comparison or `block-spike¿ scheme. Design principles and typical discriminating and logic circuits are described for the new relaying equipment. The relaying circuitry has been devised for obtaining uniform performance on all kinds of faults, by the use of two phase detectors¿one for multiphase faults and one for earth faults. The phase detector for multiphase faults provides an improved polar characteristic in the complex-impedance plane, which fits only around the fault area of a transmission line. The other features of the relay are: reliable pickup for close-in faults, least susceptibility to maloperation under power-swing conditions, and reduction in cost and panel space required. The operating characteristics of the relays, as expressed by accuracy/range charts, are also presented.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Dual-Stage Power Management Algorithms for Energy Harvesting Sensors

In this paper, we propose power management algorithms for maximizing the utility of energy harvesting sensors (EHS) that operate purely on the basis of energy harvested from the environment. In particular, we consider communication (i.e., transmission and reception) power management issues for EHS under an energy neutrality constraint. We also consider the fixed power loss effects of the circuitry, the battery inefficiency and its storage capacity, in the design of the algorithms. We propose a two-stage structure that exploits the inherent difference in the timescales at which the energy harvesting and channel fading processes evolve, without loss of optimality of the resulting solution. The outer stage schedules the power that can be used by an inner stage algorithm, so as to maximize the long term average utility and at the same time maintain energy neutrality. The inner stage optimizes the communication parameters to achieve maximum utility in the short-term, subject to the power constraint imposed by the outer stage. We optimize the algorithms for different transmission schemes such as the truncated channel inversion and retransmission strategies. The performance of the algorithms is illustrated via simulations using solar irradiance data, and for the case of Rayleigh fading channels. The results demonstrate the significant performance benefits that can be obtained using the proposed power management algorithms compared to the energy efficient (optimum when there is no storage) and the uniform power consumption (optimum when the battery has infinite capacity and is perfectly efficient) approaches.

A low-noise low-power noise-adaptive neural amplifier in 0.13um CMOS technology

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.

Photoluminescence decay rate engineering of CdSe quantum dots in ensemble arrays embedded with gold nano-antennae

We discuss experimental results on the ability to significantly tune the photoluminescence decay rates of CdSe quantum dots embedded in an ordered template, using lightly doped small gold nanoparticles (nano-antennae), of relatively low optical efficiency. We observe both enhancement and quenching of photoluminescence intensity of the quantum dots varying monotonically with increasing volume fraction of added gold nanoparticles, with respect to undoped quantum dot arrays. However, the corresponding variation in lifetime of photoluminescence spectra decay shows a hitherto unobserved, non-monotonic variation with gold nanoparticle doping. We also demonstrate that Purcell effect is quite effective for the larger (5 nm) gold nano-antenna leading to more than four times enhanced radiative rate at spectral resonance, for largest doping and about 1.75 times enhancement for off-resonance. Significantly for spectral off-resonance samples, we could simultaneously engineer reduction of non-radiative decay rate along with increase of radiative decay rate. Non-radiative decay dominates the system for the smaller (2 nm) gold nano-antenna setting the limit on how small these plasmonic nano-antennae could be to be effective in engineering significant enhancement in radiative decay rate and, hence, the overall quantum efficiency of quantum dot based hybrid photonic assemblies.

Design Of Start-up Power Circuit For Control Power Supplies With Wide Input Voltage Variation

This paper presents the design of a start up power circuit for a control power supply (CPS) which feeds power to the sub-systems of High Power Converters (HPC). The sub-systems such as gate drive card, annunciation card, protection and delay card etc; needs to be provided power for the operation of a HPC. The control power supply (CPS) is designed to operate over a wide range of input voltage from 90Vac to 270Vac. The CPS output supplies power at a desired voltage of Vout =24V to the auxiliary sub-systems of the HPC. During the starting, the power supply to the control circuitry of CPS in turn, is obtained using a separate start-up power supply. This paper discusses the various design issues of the start-up power circuit to ensure that start-up and shut down of the CPS occurs reliably. The CPS also maintains the power factor close to unity and low total harmonic distortion in input current. The paper also provides design details of gate drive circuits employed for the CPS as well as the design of on-board power supply for the CPS. Index terms: control power supply, start-up power supply, DSFC, pre-regulator