Role of corundum-adapted strains of Bacillus polymyxa in the separation of hematite and alumina

Strains of Bacillus polymyxa, preadapted and grown in the presence of corundum, were found to be capable of the efficient separation of hematite from alumina. Results of rests peformed using binary hematite-corundum and ternary hematite-quartz-corundum mixtures in the presence of cells and metabolic products separated from the adapted bacterial culture indicated that more than 99% of the hematite could he efficiently separated through selective flocculation after desliming. It was found that alumina-specific bioproteins and other nonproteinaceous compounds were secreted by bacterial cells after adaptation to the mineral. The utility of this bioprocessing is demonstrated in the removal of iron from bauxite ores through selective flocculation in the presence of the adapted bacteria.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform

In the world of high performance computing huge efforts have been put to accelerate Numerical Linear Algebra (NLA) kernels like QR Decomposition (QRD) with the added advantage of reconfigurability and scalability. While popular custom hardware solution in form of systolic arrays can deliver high performance, they are not scalable, and hence not commercially viable. In this paper, we show how systolic solutions of QRD can be realized efficiently on REDEFINE, a scalable runtime reconfigurable hardware platform. We propose various enhancements to REDEFINE to meet the custom need of accelerating NLA kernels. We further do the design space exploration of the proposed solution for any arbitrary application of size n × n. We determine the right size of the sub-array in accordance with the optimal pipeline depth of the core execution units and the number of such units to be used per sub-array.

Performance modeling and architecture exploration of network processors

This paper proposes a Petri net model for a commercial network processor (Intel iXP architecture) which is a multithreaded multiprocessor architecture. We consider and model three different applications viz., IPv4 forwarding, network address translation, and IP security running on IXP 2400/2850. A salient feature of the Petri net model is its ability to model the application, architecture and their interaction in great detail. The model is validated using the Intel proprietary tool (SDK 3.51 for IXP architecture) over a range of configurations. We conduct a detailed performance evaluation, identify the bottleneck resource, and propose a few architectural extensions and evaluate them in detail.

Biodegradation of some organic reagents from mineral process effluents

The utility of a soil microbe, namely Bacillus polymyxa, in the removal of organic reagents such as dodecylamine, ether diamine, isopropyl xanthate and sodium oleate from aqueous solutions is demonstrated. Time-bound removal of the above organic reagents from an alkaline solution was investigated under different experimental conditions during bacterial growth and in the presence of metabolites by frequent monitoring of residual concentrations as a function of time, reagent concentration and cell density. The stages and mechanisms in the biodegradation process were monitored through UV-visible and FTIR spectroscopy. Surface chemistry of the bacterial cells as well as the biosorption tendency for various organics were also established through electrokinetic and adsorption density measurements. Both the cationic amines were found to be biosorbed followed by their degradation through bacterial metabolism. The presence of the organic reagents promoted bacterial growth through effective bacterial utilization of nitrogen and carbon from the organics. Under optimal conditions, complete degradation and bioremoval of all the organics could be achieved.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Microbially induced separation of quartz from hematite using yeast cells and metabolites

The utility of yeast, Saccharomyces cerevisiae, in the separation of quartz from hematite is demonstrated. Yeast cells; as well as their metabolites, functioned as flotation collectors, depressants or flocculants and dispersants for hematite and quartz. Interaction between yeast and the above minerals resulted in significant surface chemical changes, rendering quartz surfaces hydrophobic and hematite hydrophilic. Mineral-specific extracellular proteins and exopolysaccharides were secreted by yeast cells when grown in the presence of quartz and hematite, respectively. Quartz could be efficiently separated from hematite through microbially induced flotation and selective flocculation.

A Novel Property of DNA - As a Bioflotation Reagent in Mineral Processing

Environmental concerns regarding the use of certain chemicals in the froth flotation of minerals have led investigators to explore biological entities as potential substitutes for the reagents in vogue. Despite the fact that several microorganisms have been used for the separation of a variety of mineral systems, a detailed characterization of the biochemical molecules involved therein has not been reported so far. In this investigation, the selective flotation of sphalerite from a sphalerite-galena mineral mixture has been achieved using the cellular components of Bacillus species. The key constituent primarily responsible for the flotation of sphalerite has been identified as DNA, which functions as a bio-collector. Furthermore, using reconstitution studies, the obligatory need for the presence of non-DNA components as bio-depressants for galena has been demonstrated. A probable model involving these entities in the selective flotation of sphalerite from the mineral mixture has been discussed.

Single nucleotide polymorphisms in genes that are common targets of luteotropin and luteolysin in primate corpus luteum: Computational exploration

Luteal insufficiency affects fertility and hence study of mechanisms that regulate corpus luteum (CL) function is of prime importance to overcome infertility problems. Exploration of human genome sequence has helped to study the frequency of single nucleotide polymorphisms (SNPs). Clinical benefits of screening SNPs in infertility are being recognized well in recent times. Examining SNPs in genes associated with maintenance and regression of CL may help to understand unexplained luteal insufficiency and related infertility. Publicly available microarray gene expression databases reveal the global gene expression patterns in primate CL during the different functional state. We intend to explore computationally the deleterious SNPs of human genes reported to be common targets of luteolysin and luteotropin in primate CL Different computational algorithms were used to dissect out the functional significance of SNPs in the luteinizing hormone sensitive genes. The results raise the possibility that screening for SNPs might be integrated to evaluate luteal insufficiency associated with human female infertility for future studies. (C) 2012 Elsevier B.V. All rights reserved,