Frequency characteristics of very fast transient currents in a 245-kV GIS

The conducted as well as the induced voltages on control cables and control circuits due to transient electromagnetic (EM) fields generated during switching operations in a gas-insulated substation (GIS) depend on the waveshape of the very fast transient overvoltages and the associated very-fast transient currents (VFTCs). The aim of this paper is to build a basis for characterizing the VFTC generated in gas-insulated switchgear and the,associated equipment during switching operations for the study of transient coupling phenomena. The peak magnitudes of VFTC and their dominant frequency content at various locations have been computed in a 245-kV GIS for different switching operations as well as substation configurations. Finally, the influence of the substation layout on the frequency spectrum, dominant frequencies, and the highest possible frequency component of the VFTC at various distances from the switch have been reported.

Design of rectangular reinforced concrete slabs supported on all the sides with a short discontinuous edge

Bending moment coefficients for the design of rectangular reinforced concrete panels supported on four sides with a short discontinuous edge are derived using the strip theory. The moment fields resulting from the use of proposed coefficients are examined in terms of the moment volume for possible savings in reinforcement and compared with other codified procedures. The strip coefficients averaged over the corresponding sides of the panel, besides resulting in considerable savings in reinforcement, are found to be identical with the coefficients predicted by simple yield line theory using an orthotropic layout of reinforcement.

Polypyrimidine tract-binding protein interacts with coxsackievirus B3 RNA and influences its translation

We have investigated the possible role of trans-acting factors interacting with the untranslated regions (UTRs) of coxsackievirus B3 (CVB3) RNA. We show here that polypyrimidine tract-binding protein (PTB) binds specifically to both 5' and 3' UTRs, but with different affinity. We have demonstrated that PTB is a bona fide internal ribosome entry site (IRES) trans-acting factor (ITAF) for CVB3 RNA by characterizing the effect of partial silencing of FIB ex vivo in He La cells. Furthermore, IRES activity in BSC-1 cells, which are reported to have a very low level of endogenous FIB, was found to be significantly lower than that in He La cells. Additionally, we have mapped the putative contact points of PTB on the 5' and 3' UTRs by an RNA toe-printing assay. We have shown that the 3' UTR is able to stimulate CVB3 IRES-mediated translation. Interestingly, a deletion of 15 nt at the 5' end or 14 rut at the 3' end of the CVB3 3' UTR reduced the 3' UTR-mediated enhancement of IRES activity ex vivo significantly, and a reduced interaction was shown with PTB. It appears that the FIB protein might help in circularization of the CVB3 RNA by bridging the ends necessary for efficient translation of the viral RNA.

Moment-Matched Lognormal Modeling of Uplink Interference with Power Control and Cell Selection

We develop an alternate characterization of the statistical distribution of the inter-cell interference power observed in the uplink of CDMA systems. We show that the lognormal distribution better matches the cumulative distribution and complementary cumulative distribution functions of the uplink interference than the conventionally assumed Gaussian distribution and variants based on it. This is in spite of the fact that many users together contribute to uplink interference, with the number of users and their locations both being random. Our observations hold even in the presence of power control and cell selection, which have hitherto been used to justify the Gaussian distribution approximation. The parameters of the lognormal are obtained by matching moments, for which detailed analytical expressions that incorporate wireless propagation, cellular layout, power control, and cell selection parameters are developed. The moment-matched lognormal model, while not perfect, is an order of magnitude better in modeling the interference power distribution.

Grid interfacing of a photovoltaic system using a chain cell converter

With the rapid development of photovoltaic system installations and increased number of grid connected power systems, it has become imperative to develop an efficient grid interfacing instrumentation suitable for photovoltaic systems ensuring maximum power transfer. The losses in the power converter play an important role in the overall efficiency of a PV system. Chain cell converter is considered to be efficient as compared to PWM converters due to lower switching losses, modularized circuit layout, reduced voltage rating of the converter switches, reduced EMI. The structure of separate dc sources in chain cell converter is well suited for photovoltaic systems as there will b several separate PV modules in the PV array which can act as an individual dc source. In this work, a single phase multilevel chain cell converter is used to interface the photovoltaic array to a single phase grid at a frequency of 50Hz. Control algorithms are developed for efficient interfacing of the PV system with grid and isolating the PV system from grid under faulty conditions. Digital signal processor TMS320F 2812 is used to implement the control algorithms developed and for the generation of other control signals.

Structural alteration from non-B to B-form could reflect DNase I hypersensitivity

Preferential cleavage of active genes by DNase I has been correlated with a structurally altered conformation of DNA at the hypersensitive site in chromatin. To have a better understanding of the structural requirements for gene activation as probed by DNase I action, digestability by DNase I of synthetic polynucleotides having the ability to adopt B and non-B conformation (like Z-form) was studied which indicated a marked higher digestability of the B-form of DNA. Left handed Z form present within a natural sequence in supercoiled plasmid also showed marked resistance towards DNase I digestion. We show that alternating purine-pyrimidine sequences adopting Z-conformation exhibit DNAse I foot printing even in a protein free system. The logical deductions from the results indicate that 1) altered structure like Z-DNA is not a favourable substrate for DNase I, 2) both the ends of the alternating purine-pyrimidine insert showed hypersensitivity, 3) B-form with a minor groove of 12-13 A is a more favourable substrate for DNase I than an altered structure, 4) any structure of DNA deviating largely from B form with a capacity to flip over to the B-form are potential targets for the DNase I enzymic probes in naked DNA.

An optimal parallel algorithm for sparse matrix bandwidth reduction on a linear array

A simple and efficient algorithm for the bandwidth reduction of sparse symmetric matrices is proposed. It involves column-row permutations and is well-suited to map onto the linear array topology of the SIMD architectures. The efficiency of the algorithm is compared with the other existing algorithms. The interconnectivity and the memory requirement of the linear array are discussed and the complexity of its layout area is derived. The parallel version of the algorithm mapped onto the linear array is then introduced and is explained with the help of an example. The optimality of the parallel algorithm is proved by deriving the time complexities of the algorithm on a single processor and the linear array.

Isolation and characterization of riboflavin carrier protein from human amniotic fluid

A specific protein exhibiting immunological cross-reactivity with chicken riboflavin carrier protein has been purified to homogeneity from human amniotic fluid by use of ion-exchange and affinity chromatography. The protein is similar to its avian counterpart in terms of molecular size, distribution of 125I-labelled tryptic peptides during finger printing, and preferential binding to riboflavin. Immunologically, they are homologous since most of the monoclonal antibodies raised against the avian protein cross-react with the purified human vitamin carrier.

Improving web server performance by network aware data buffering and caching

In this paper we propose a new method of data handling for web servers. We call this method Network Aware Buffering and Caching (NABC for short). NABC facilitates reduction of data copies in web server's data sending path, by doing three things: (1) Layout the data in main memory in a way that protocol processing can be done without data copies (2) Keep a unified cache of data in kernel and ensure safe access to it by various processes and kernel and (3) Pass only the necessary meta data between processes so that bulk data handling time spent during IPC can be reduced. We realize NABC by implementing a set of system calls and an user library. The end product of the implementation is a set of APIs specifically designed for use by the web servers. We port an in house web server called SWEET, to NABC APIs and evaluate performance using a range of workloads both simulated and real. The results show a very impressive gain of 12% to 21% in throughput for static file serving and 1.6 to 4 times gain in throughput for lightweight dynamic content serving for a server using NABC APIs over the one using UNIX APIs.

Photoelectron spectroscopy beamline on Indus-1 synchrotron radiation source

We describe here a photoelectron spectroscopy beamline installed on Indus-1 storage ring. Initially we give a brief description of optical and mechanical layout of beam-line. The beamline optics was designed to cover energy range from 10 eV to 200 eV and it consists of a pre-focusing mirror, a toroidal grating monochromator and a post-focusing mirror. We then discuss indigenously developed ultra high vacuum compatible work station to carry out angle integrated photoemission experiments. The beamline has been successfully commissioned and photoemission measurements on a variety of standard samples are presented.

Photo-Defined Electrically Assisted Etching Method for Metal Stencil Fabrication

Metal stencils are well known in electronics printing application such as for dispensing solder paste for surface mounting, printing embedded passive elements in multilayer structures, etc. For microprinting applications using stencils, the print quality depends on the smoothness of the stencil aperture and its dimensional accuracy, which in turn are invariably related to the method used to manufacture the stencils. In this paper, fabrication of metal stencils using a photo-defined electrically assisted etching method is described. Apertures in the stencil were made in neutral electrolyte using three different types of impressed current, namely, dc, pulsed dc, and periodic pulse reverse (PPR). Dimensional accuracy and wall smoothness of the etched apertures in each of the current waveforms were compared. Finally, paste transfer efficiency of the stencil obtained using PPR was calculated and compared with those of a laser-cut electropolished stencil. It is observed that the stencil fabricated using current in PPR waveform has better dimensional accuracy and aperture wall smoothness than those obtained with dc and pulsed dc. From the paste transfer efficiency experiment, it is concluded that photo-defined electrically assisted etching method can provide an alternate route for fabrication of metal stencils for future microelectronics printing applications.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

A Low Power Frequency Multiplication Technique for Zigbee Transceiver

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405-2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LC-VCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-mum RF process with spiral on-chip inductors and MIM (metal-insulator-metal) capacitor option.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

In this paper we propose the architecture of a SoC fabric onto which applications described in a HLL are synthesized. The fabric is a homogeneous layout of computation, storage and communication resources on silicon. Through a process of composition of resources (as opposed to decomposition of applications), application specific computational structures are defined on the fabric at runtime to realize different modules of the applications in hardware. Applications synthesized on this fabric offers performance comparable to ASICs while retaining the programmability of processing cores. We outline the application synthesis methodology through examples, and compare our results with software implementations on traditional platforms with unbounded resources.