Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor

In this paper, a physically based analytical quantum linear threshold voltage model for short channel quad gate MOSFETs is developed. The proposed model, which is suitable for circuit simulation, is based on the analytical solution of 3-D Poisson and 2-D Schrodinger equation. Proposed model is fully validated against the professional numerical device simulator for a wide range of device geometries and also used to analyze the effect of geometry variation on the threshold voltage.

Probing Single and Bilayer Graphene Field Effect Transistors By Raman Spectroscopy

This article is a review of our work related to Raman studies of single layer and bilayer graphenes as a function Fermi level shift achieved by electrochemically top gating a field effect transistor. Combining the transport and in situ Raman studies of the field effect devices, a quantitative understanding is obtained of the phonon renormalization due to doping of graphene. Results are discussed in the light of time dependent perturbation theory, with electron phonon coupling parameter as an input from the density functional theory. It is seen that phonons near and Gamma and K points of the Brillouin zone are renormalized very differently by doping. Further, Gamma-phonon renormalization is different in bilayer graphene as compared to single layer, originating from their different electronic band structures near the zone boundary K-point. Thus Raman spectroscopy is not only a powerful probe to characterize the number of layers and their quality in a graphene sample, but also to quantitatively evaluate electron phonon coupling required to understand the performance of graphene devices.

High On-Off Ratio Bilayer Graphene Complementary Field Effect Transistors

In this paper, we propose a novel S/D engineering for dual-gated Bilayer Graphene (BLG) Field Effect Transistor (FET) using doped semiconductors (with a bandgap) as source and drain to obtain unipolar complementary transistors. To simulate the device, a self-consistent Non-Equilibrium Green's Function (NEGF) solver has been developed and validated against published experimental data. Using the simulator, we predict an on-off ratio in excess of 10(4) and a subthreshold slope of similar to 110mV/decade with excellent scalability and current saturation, for a 20nm gate length unipolar BLG FET. However, the performance of the proposed device is found to be strongly dependent on the S/D series resistance effect. The obtained results show significant improvements over existing reports, marking an important step towards bilayer graphene logic devices.

An ultra-stable Cu nanowire under thermo-mechanical loading: A molecular dynamic study

We report on the formation of a stable Body-Centered Heptahedral (BCH) crystalline nanobridge structure of diameter ~ 1nm under high strain rate tensile loading to a <100> Cu nanowire. Extensive Molecular Dynamics (MD) simulations are performed. Six different cross-sectional dimensions of Cu nanowires are analyzed, i.e. 0.3615 x 0.3615 nm2, 0.723 x 0.723 nm2, 1.0845 x 1.0845 nm2, 1.446 x 1.446 nm2, 1.8075 x 1.8075 nm2, and 2.169 x 2.169 nm2. The strain rates used in the present simulations are 1 x 109 s-1, 1 x 108 s-1, and 1 x 107 s-1. We have shown that the length of the nanobridge can be characterized by larger plastic strain. A large plastic deformation is an indication that the structure is highly stable. The BCH nanobridge structure also shows enhanced mechanical properties such as higher fracture toughness and higher failure strain. The effect of temperature, strain rate and size of the nanowire on the formation of BCH structure is also explained in details. We also show that the initial orientation of the nanowires play an important role on the formation of BCH crystalline structure. Results indicate that proper tailoring of temperature and strain rate during processing or in the device can lead to very long BCH nanobridge structure of Cu with enhanced mechanical properties, which may find potential application for nano-scale electronic circuits.

Size and temperature dependent stability and phase transformation in single-crystal zirconium nanowire

A novel size dependent FCC (face-centered-cubic) -> HCP (hexagonally-closed-pack) phase transformation and stability of an initial FCC zirconium nanowire are studied. FCC zirconium nanowires with cross-sectional dimensions < 20 are found unstable in nature, and they undergo a FCC -> HCP phase transformation, which is driven by tensile surface stress induced high internal compressive stresses. FCC nanowire with cross-sectional dimensions > 20 , in which surface stresses are not enough to drive the phase transformation, show meta-stability. In such a case, an external kinetic energy in the form of thermal heating is required to overcome the energy barrier and achieve FCC -> HCP phase transformation. The FCC-HCP transition pathway is also studied using Nudged Elastic Band (NEB) method, to further confirm the size dependent stability/metastability of Zr nanowires. We also show size dependent critical temperature, which is required for complete phase transformation of a metastable-FCC nanowire.

Nature of Electronic States in Atomically Thin MoS(2) Field-Effect Transistors

We present low-temperature electrical transport experiments in five field-effect transistor devices consisting of monolayer, bilayer, and trilayer MoS(2) films, mechanically exfoliated onto Si/SiO(2) substrate. Our experiments reveal that the electronic states In all films are localized well up to room temperature over the experimentally accessible range of gate voltage. This manifests in two-dimensional (2D) variable range hopping (VRH) at high temperatures, while below similar to 30 K, the conductivity displays oscillatory structures In gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T(0)) of VRH and gate voltage dependence of conductivity, we suggest that Coulomb potential from trapped charges In the substrate is the dominant source of disorder in MoS(2) field-effect devices, which leads to carrier localization, as well.

Influence of Gate Corrugations on the Performance of Thin-Film Transistors

This letter investigates the influence of a corrugated gate on the transfer characteristics of thin-film transistors. Corrugations that run parallel to the length of the channel from source to drain are patterned on the gate. The author finds that these corrugations result in higher currents as compared to conventional planar-gate transistors.

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Temperature-pressure-induced solid-solid < 100 > to < 110 > reorientation in FCC metallic nanowire: a molecular dynamic study

Atomistic simulation of initial < 100 > oriented FCC Cu nanowires shows a novel coupled temperature-pressure dependent reorientation from < 100 > to < 110 > phase. A temperature-pressure-induced solid-solid < 100 > to < 110 > reorientation diagram is generated for Cu nanowire with varying cross-sectional sizes. A critical pressure is reported for Cu nanowires with varying cross-sectional sizes, above which an initial < 100 > oriented nanowire shows temperature independent reorientation into the < 110 > phase. The effect of surface stresses on the < 100 > to < 110 > reorientation is also studied. The results indicate that above a critical cross-sectional size for a given temperature-pressure, < 100 > to < 110 > reorientation is not possible. It is also reported here that for a given applied pressure, an increase in temperature is required for the < 100 > to < 110 > reorientation with increasing cross-sectional size of the nanowire. The temperature-pressure-induced solid-solid < 100 > to < 110 > reorientation diagram reported in the present paper could further be used as guidelines for controlling the reorientations/shape memory in nano-scale applications of FCC metallic nanowires.

Solution processable quinoxaline based molecular materials for organic field effect transistors

Three new solution processable quinoxaline based donor-acceptor-donor (D-A-D) type molecules have been synthesized for application in field effect transistors. These molecules were characterized by UV-visible spectroscopy, thermal gravimetric analysis, differential scanning calorimetry and cyclic voltammetry. DFT calculation gives deeper insight into the electronic structure of these molecules. The crystallinity and morphology features of thin film were investigated using X-ray diffraction. These molecules show liquid crystalline phase confirmed by DSC and optical polarizing microscopy. Investigation of their field effect transistor performance indicated that these molecules exhibited p-type mobility up to 9.7 x 10 (4) cm(2) V (1) s (1) and on/off ratio of 10(4). (C) 2012 Elsevier B.V. All rights reserved.

Analytical Field-Effect Method for Extraction of Subgap States in Thin-Film Transistors

We present an analytical field-effect method to extract the density of subgap states (subgap DOS) in amorphous semiconductor thin-film transistors (TFTs), using a closed-form relationship between surface potential and gate voltage. By accounting the interface states in the subthreshold characteristics, the subgap DOS is retrieved, leading to a reasonably accurate description of field-effect mobility and its gate voltage dependence. The method proposed here is very useful not only in extracting device performance but also in physically based compact TFT modeling for circuit simulation.