134 resultados para Hardware Transactional Memory


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Using the promeasure technique, we give an alternative evaluation of a path integral corresponding to a quadratic action with a generalized memory.

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Low frequency fluctuations in the electrical resistivity, or noise, have been used as a sensitive tool to probe into the temperature driven martensite transition in dc magnetron sputtered thin films of nickel titanium shape-memory alloys. Even in the equilibrium or static case, the noise magnitude was more than nine orders of magnitude larger than conventional metallic thin films and had a characteristic dependence on temperature. We observe that the noise while the temperature is being ramped is far larger as compared to the equilibrium noise indicating the sensitivity of electrical resistivity to the nucleation and propagation of domains during the shape recovery. Further, the higher order statistics suggests the existence of long range correlations during the transition. This new characterization is based on the kinetics of disorder in the system and separate from existing techniques and can be integrated to many device applications of shape memory alloys for in-situ shape recovery sensing.

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The design, implementation and evaluation are described of a dual-microcomputer system based on the concept of shared memory. Shared memory is useful for passing large blocks of data and it also provides a means to hold and work with shared data. In addition to the shared memory, a separate bus between the I/O ports of the microcomputers is provided. This bus is utilized for interprocessor synchronization. Software routines helpful in applying the dual-microcomputer system to realistic problems are presented. Performance evaluation of the system is carried out using benchmarks.

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The microcommands constituting the microprogram of the control memory of a microprogrammed processor can be partitioned into a number of disjoint sets. Some of these sets are then encoded to minimize the word width of the ROM storing the microprogram. A further reduction in the width of the ROM words can be achieved by a technique known as bit steering where one or more bits are shared by two or more sets of microcommands. These sets are called the steerable sets. This correspondence presents a simple method for the detection and encoding of steerable sets. It has been shown that the concurrency matrix of two steerable sets exhibits definite patterns of clusters which can be easily recognized. A relation "connection" has been defined which helps in the detection of three-set steerability. Once steerable sets are identified, their encoding becomes a straightforward procedure following the location of the identifying clusters on the concurrency matrix or matrices.

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An experimental investigation into the ambient temperature, load-controlled tension�tension fatigue behavior of a martensitic Nitinol shape memory alloy (SMA) was conducted. Fatigue life for several stress levels spanning the critical stress for detwinning was determined and compared with that obtained on an alloy similar in composition but in the austenitic state at room temperature. Results show that the fatigue life of the pseudo-plastic alloy is superior to superelastic shape memory alloy. The stress�strain hysteretic response, monitored throughout the fatigue loading, reveals progressive strain accumulation with the cyclic loading. In addition, the area of hysteresis and recoverable and frictional energies were found to decrease with increasing number of fatigue cycles. Post-mortem characterization of the fatigued specimens through calorimetry and fractography was conducted in order to get further insight into the fatigue micromechanisms. These results are discussed in terms of reversible and irreversible microstructural changes that take place during cyclic loading. Aspects associated with self-heating of martensitic alloy undergoing high frequency stress cycling are discussed.

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Crack loading and crack extension in pseudoelastic binary NiTi shape memory alloy (SMA) miniature compact tension (CT) specimens with 50.7 at.% Ni (austenitic, pseudoelastic) was investigated using infrared (IR) thermography during in situ loading and unloading. IR thermographic measurements allow for the observation of heat effects associated with the stress-induced transformation of martensite from B2 to BIT during loading and the reverse transformation during unloading. The results are compared with optical images and discussed in terms of the crack growth mechanisms in pseudoelastic NiTi SMAs. Direct experimental evidence is presented which shows that crack growth occurs into a stress-induced martensitic microstructure, which immediately retransforms to austenite in the wake of the crack.

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We employ a fluctuation-based technique to investigate the athermal component associated with martensite phase transition, which is a prototype of temperature-driven structural transformation. Statistically, when the phase transition is purely athermal, we find that the temporal sequence of avalanches under constant drive is insensitive to the drive rate. We have used fluctuations in electrical resistivity or noise in nickel titanium shape memory alloys in three different forms: a thin film exhibiting well-defined transition temperatures,a highly disordered film, and a bulk wire of rectangular cross-section. Noise is studied in the realm of dynamic transition,viz.while the temperature is being ramped, which probes into the kinetics of the transformation at real time scales,and could probably stand out as a promising tool for material testing in various other systems, including nanoscale devices.

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The β-phase aging response of Cu–Al–Ni single crystal shape memory alloys (SMAs) within the temperature range of 473–573 K has been investigated. Alloys in austenitic (Cu–14.1Al–4Ni wt.%, alloy A) and martensitic (Cu–13.4Al–4Ni wt.%, alloy M) conditions at room temperature were considered. Aged samples show presence of β1′ and γ1′ martensites in both the alloys and formation of γ2 precipitates in the alloy A. The differential scanning calorimetry (DSC) thermograms of the aged samples show increase in transformation temperatures as well as transformation hysteresis with aging. Dynamic mechanical analysis (DMA) was conducted on both the alloys to ascertain the role of precipitates and martensitic transition on tan δ, which characterizes the damping behaviour of the material. With aging, a steady decrease in tan δ value was observed in both the alloys, which was attributed to the decrease in the number of interfaces per unit area with increasing aging temperature. Moreover, in alloy A, as the volume fraction of precipitate increases with aging, the movement of martensitic interfaces is restricted causing a decreased tan δ.

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The relay hypothesis [R. Nayak, S. Mitra-Kaushik, M.S. Shaila, Perpetuation of immunological memory: a relay hypothesis, Immunology 102 (2001) 387-395] was earlier proposed to explain perpetuation of immunological memory without requiring long lived memory cells or persisting antigen. This hypothesis envisaged cycles of interaction and proliferation of complementary idiotypic B cells (Burnet cells) and anti-idiotypic B cells (Jerne cells) as the primary reason for perpetuation of immunological memory. The presence of pepti-domimics of antigen in anti-idiotypic antibody and their presentation to antigen specific T cells was postulated to be primary reason for perpetuation of T cell memory. Using a viral hemagglutinin as a model, in this work, we demonstrate the presence of peptidomimics in the variable region of ail anti-idiotypic antibody capable of functionally mimicking the antigen derived peptides. A CD8(+) CTL clone was generated against the hemagglutinin protein which specifically responds to either peptidomimic synthesizing cells or peptidomimic pulsed antigen presenting cells. Thus, it appears reasonable that a population of activated antigen specific T cells is maintained in the body by presentation of peptidomimic through Jerne cells and other antigen presenting cells long after immunization. (C) 2007 Elsevier Inc. All rights reserved.

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Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri net model of IP forwarding application on IXP2400 that models the different levels of the memory hierarchy. The cell based interface used to receive and transmit packets in a network processor leads to some small size DRAM accesses. Such narrow accesses to the DRAM expose the bank access latency, reducing the bandwidth that can be realized. With real traces up to 30% of the accesses are smaller than the cell size, resulting in 7.7% reduction in DRAM bandwidth. To overcome this problem, we propose buffering these small chunks of data in the on chip scratchpad memory. This scheme also exploits greater degree of parallelism between different levels of the memory hierarchy. Using real traces from the internet, we show that the transmit rate can be improved by an average of 21% over the base scheme without the use of additional hardware. Further, the impact of different traffic patterns on the network processor resources is studied. Under real traffic conditions, we show that the data bus which connects the off-chip packet buffer to the micro-engines, is the obstacle in achieving higher throughput.

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A major concern of embedded system architects is the design for low power. We address one aspect of the problem in this paper, namely the effect of executable code compression. There are two benefits of code compression – firstly, a reduction in the memory footprint of embedded software, and secondly, potential reduction in memory bus traffic and power consumption. Since decompression has to be performed at run time it is achieved by hardware. We describe a tool called COMPASS which can evaluate a range of strategies for any given set of benchmarks and display compression ratios. Also, given an execution trace, it can compute the effect on bus toggles, and cache misses for a range of compression strategies. The tool is interactive and allows the user to vary a set of parameters, and observe their effect on performance. We describe an implementation of the tool and demonstrate its effectiveness. To the best of our knowledge this is the first tool proposed for such a purpose.

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In prediction phase, the hierarchical tree structure obtained from the test image is used to predict every central pixel of an image by its four neighboring pixels. The prediction scheme generates the predicted error image, to which the wavelet/sub-band coding algorithm can be applied to obtain efficient compression. In quantization phase, we used a modified SPIHT algorithm to achieve efficiency in memory requirements. The memory constraint plays a vital role in wireless and bandwidth-limited applications. A single reusable list is used instead of three continuously growing linked lists as in case of SPIHT. This method is error resilient. The performance is measured in terms of PSNR and memory requirements. The algorithm shows good compression performance and significant savings in memory. (C) 2006 Elsevier B.V. All rights reserved.

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In this paper we first present the 'wet N2O' furnace oxidation process to grow nitrided tunnel oxides in the thickness range 6 to 8 nm on silicon at a temperature of 800 degrees C. Electrical characteristics of MOS capacitors and MOSFETs fabricated using this oxide as gate oxide have been evaluated and the superior features of this oxide are ascertained The frequency response of the interface states, before and after subjecting the MOSFET gate oxide to constant current stress, is studied using a simple analytical model developed in this work.

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We develop several hardware and software simulation blocks for the TinyOS-2 (TOSSIM-T2) simulator. The choice of simulated hardware platform is the popular MICA2 mote. While the hardware simulation elements comprise of radio and external flash memory, the software blocks include an environment noise model, packet delivery model and an energy estimator block for the complete system. The hardware radio block uses the software environment noise model to sample the noise floor. The packet delivery model is built by establishing the SNR-PRR curve for the MICA2 system. The energy estimator block models energy consumption by Micro Controller Unit(MCU), Radio, LEDs, and external flash memory. Using the manufacturerpsilas data sheets we provide an estimate of the energy consumed by the hardware during transmission, reception and also track several of the MCUs states with the associated energy consumption. To study the effectiveness of this work, we take a case study of a paper presented in [1]. We obtain three sets of results for energy consumption through mathematical analysis, simulation using the blocks built into PowerTossim-T2 and finally laboratory measurements. Since there is a significant match between these result sets, we propose our blocks for T2 community to effectively test their application energy requirements and node life times.

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Understanding the molecular mechanisms of immunological memory assumes importance in vaccine design. We had earlier hypothesized a mechanism for the maintenance of immunological memory through the operation of a network of idiotypic and anti-idiotypic antibodies (Ab2). Peptides derived from an internal image carrying anti-idiotypic antibody are hypothesized to facilitate the perpetuation of antigen specific T cell memory through similarity in peptide-MHC binding as that of the antigenic peptide. In the present work, the existence of such peptidomimics of the antigen in the Ab2 variable region and their similarity of MHC-I binding was examined by bioinformatics approaches. The analysis employing three known viral antigens and one tumor-associated antigen shows that peptidomimics from Ab2 variable regions have structurally similar MHC-I binding patterns as compared to antigenic peptides, indicating a structural basis for memory perpetuation. (C)) 2007 Elsevier Inc. All rights reserved.