Programming an FPGA to Emulate the Dynamics of DC Machines

This paper presents the programming an FPGA (Field Programmable Gate Array) to emulate the dynamics of DC machines. FPGA allows high speed real time simulation with high precision. The described design includes block diagram representation of DC machine, which contain all arithmetic and logical operations. The real time simulation of the machine in FPGA is controlled by user interfaces they are Keypad interface, LCD display on-line and digital to analog converter. This approach provides emulation of electrical machine by changing the parameters. Separately Exited DC machine implemented and experimental results are presented.

Neutral-point balancing of neutral-point-clamped three-level inverter with a front end switched rectifier DC source for the full modulationn range

A switched rectifier DC voltage source three-level neutral-point-clamped (NPC) converter topology is proposed here to alleviate the inverter from capacitor voltage balancing in three-level drive systems. The proposed configuration requires only one DC link with a voltage of half of that needed in a conventional NPC inverter. To obtain a rated DC link voltage, the rectifier DC source is alternately connected in parallel to one of the two series capacitors using two switches and two diodes with device voltage ratings of half the total DC bus voltage. The frequency at which the voltage source is switched is independent of the inverter and will not affect its operation since the switched voltage source in this configuration balances the capacitors automatically. The proposed configuration can also be used as a conventional two-level inverter in the lower modulation index range, thereby increasing the reliability of the drivesystem. A space-vector-based PWM scheme is used to verify this proposed topology on a laboratory system.

A unified model for auxiliary switch commutated DC-DC converters

A novel ZVS auxiliary switch commutated variation for all DGDC converter topologies has been proposed in 2006. With proper designation of the circuit variables (throw current I and the pole voltage V), all these converters are seen to be governed by an identical set of equations. With idealized switches, the steady-state performance is obtainable in an analytical form. The conversion ratio of the converter topologies is obtained. A generalized equivalent circuit emerges for all these converters from the steady-state conversion ratio. It also provides a dynamic model as well. With these generalized steady-state equivalent circuits, small signal analysis of these converters may be carried out readily. It enables one to use the familiar state space averaged results of the standard PWM DGDC converters for the resonant counterparts. Th dc and ac models reveals that dc and low frequency behaviour of the proposed family of converters is similiar to that of its PWM parent

Steady-State Stability of Current Mode Active-Clamp ZVS DC-DC Converters

Active-clamp dc-dc converters are pulsewidth-modulated converters having two switches featuring zero-voltage switching at frequencies beyond 100 kHz. Generalized equivalent circuits valid for steady-state and dynamic performance have been proposed for the family of active-clamp converters. The active-clamp converter is analyzed for its dynamic behavior under current control in this paper. The steady-state stability analysis is presented. On account of the lossless damping inherent in the active-clamp converters, it appears that the stability region in the current-controlled active-clamp converters get extended for duty ratios, a little greater than 0.5, unlike in conventional hard-switched converters. The conventional graphical approach fails to assess the stability of current-controlled active-clamp converters due to the coupling between the filter inductor current and resonant inductor current. An analysis that takes into account the presence of the resonant elements is presented to establish the condition for stability. This method correctly predicts the stability of the current-controlled active-clamp converters. A simple expression for the maximum duty cycle for subharmonic free operation is obtained. The results are verified experimentally.

A structure-preserving energy function for stability analysis of AC/DC systems

Direct stability analysis ofAC/DC power systems using a structure-preserving energy function (SPEF) is proposed in this paper. The system model considered retains the load buses thereby enabling the representation of nonlinear voltage dependent loads. TheHVDC system is represented with the same degree of detail as is normally done in transient stability simulation. The converter controllers can be represented by simplified or detailed models. Two or multi-terminalDC systems can be considered. The stability analysis is illustrated with a 3-machine system example and encouraging results have been obtained.

Dynamic analysis of voltage instability in AC-DC systems

This paper presents the analysis and study of voltage collapse at any converter bus in A C-DC systems considering the dynamics of DC system. The problem of voltage instability is acute when HVDC links are connected to weak AC systems, the strength determined by short circuit ratio (SCR) at the converter bus. The converter control strategies are important in determining voltage instability. Small signal analysis is used to identify critical modes and evaluate the effect of AC system strength and control parameters. A sample two-terminal DC system is studied and the results compared with those obtained from static analysis. Also, the results obtained from small signal analysis are validated with nonlinear simulation.

Digital Deadbeat Control Tuning for dc-dc Converters Using Error Correlation

This letter proposes a simple tuning algorithm for digital deadbeat control based on error correlation. By injecting a square-wave reference input and calculating the correlation of the control error, a gain correction for deadbeat control is obtained. The proposed solution is simple, it requires a short tuning time, and it is suitable for different DC-DC converter topologies. Simulation and experimental results on synchronous buck converters confirm the properties of the proposed tuning algorithm.

Steady-State Stability of Current-Mode Active-Clamp ZVS DC-DC Converters

Active-clamp dc-dc converters are pulsewidth-modulated converters having two switches featuring zero-voltage switching at frequencies beyond 100 kHz. Generalized equivalent circuits valid for steady-state and dynamic performance have been proposed for the family of active-clamp converters. The active-clamp converter is analyzed for its dynamic behavior under current control in this paper. The steady-state stability analysis is presented. On account of the lossless damping inherent in the active-clamp converters, it appears that the stability region in the current-controlled active-clamp converters get extended for duty ratios, a little greater than 0.5 unlike in conventional hard-switched converters. The conventional graphical approach fails to assess the stability of current-controlled active-clamp converters, due to the coupling between the filter inductor current and resonant inductor current. An analysis that takes into account the presence of the resonant elements is presented to establish the condition for stability. This method correctly predicts the stability of the current-controlled active-clamp converters. A simple expression for the maximum duty cycle for subharmonic-free operation is obtained. The results are verified experimentally.

Input voltage modulated high voltage DC power supply topology for pulsed load applications

High voltage power supplies for radar applications are investigated which are subjected to pulsed load with stringent specifications. In the proposed solution, power conversion is done in two stages. A low power-high frequency converter modulates the input voltage of a high power-low frequency converter. This method satisfies all the performance specifications and takes care of the critical aspects of HV transformer.

Beat frequency oscillations in the output voltage of high voltage DC power supplies under pulsed loading

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. Few converter topologies are proposed to tackle these problems. A study is made regarding the beat frequency oscillations that may exist with pulsed loading. It is illustrated with respect to the proposed converter topologies. Methods are proposed to eliminate or minimize these oscillations.

A Three-Level Common-Mode Voltage Eliminated Inverter With Single DC Supply Using Flying Capacitor Inverter and Cascaded H-Bridge

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc.

A Reduced Device-Count Hybrid Multilevel Inverter Topology with single DC Source and Improved Fault Tolerance

A new hybrid multilevel power converter topology is presented in this paper. The proposed power converter topology uses only one DC source and floating capacitors charged to asymmetrical voltage levels, are used for generating different voltage levels. The SVPWM based control strategy used in this converter maintains the capacitor voltages at the required levels in the entire modulation range including the over-modulation region. For the voltage levels: nine and above, the number of components required in the proposed topology is significantly lower, compared to the conventional multilevel inverter topologies. The number of capacitors required in this topology reduces drastically compared to the conventional flying capacitor topology, when the number of levels in the inverter output increases. This topology has better fault tolerance, as it is capable of operating with reduced number of levels, in the entire modulation range, in the event of any failure in the H-bridges. The transient as well as the steady state performance of the nine-level version of the proposed topology is experimentally verified in the entire modulation range including the over-modulation region.

A Seventeen-level Inverter With a Single DC-link For Motor Drives

In the present paper, a novel topology for generating a 17-level inverter using three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors. The proposed circuit is analyzed and various aspects of it are presented in the paper. This circuit is experimentally verified and the results are shown. The stability of the capacitor balancing algorithm has been verified during sudden acceleration. This circuit has many pole voltage redundancies. This circuit has an advantage of balancing all the capacitor voltages instantaneously by switching through the redundancies. Another advantage of this topology is its ability to generate all the 17 pole voltages from a single DC link which enables back to back converter operation. Also, the proposed inverter can be operated at all load power factors and modulation indices. Another advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels.

Low-frequency dc bus ripple cancellation in single phase pulse-width modulation inverters

This study presents a topology for a single-phase pulse-width modulation (PWM) converter which achieves low-frequency ripple reduction in the dc bus even when there are grid frequency variations. A hybrid filter is introduced to absorb the low-frequency current ripple in the dc bus. The control strategy for the proposed filter does not require the measurement of the dc bus ripple current. The design criteria for selecting the filter components are also presented in this study. The effectiveness of the proposed circuit has been tested and validated experimentally. A smaller dc-link capacitor is sufficient to keep the low-frequency bus ripple to an acceptable range in the proposed topology.

Experimental results on low cost microcontroller based DC drive implementation

This paper presents the experimental results for an attractive control scheme implementation using an 8 bit microcontroller. The power converter involved is a 3 phase full controlled bridge rectifier. A single quadrant DC drive has been realized and results have been presented for both open and closed loop implementations.