BER analysis of space-time block codes from generalized complex orthogonal designs for M-PSK

In this paper, we present an analysis for the bit error rate (BER) performance of space-time block codes (STBC) from generalized complex orthogonal designs for M-PSK modulation. In STBCs from complex orthogonal designs (COD), the norms of the column vectors are the same (e.g., Alamouti code). However, in generalized COD (GCOD), the norms of the column vectors may not necessarily be the same (e.g., the rate-3/5 and rate-7/11 codes by Su and Xia in [1]). STBCs from GCOD are of interest because of the high rates that they can achieve (in [2], it has been shown that the maximum achievable rate for STBCs from GCOD is bounded by 4/5). While the BER performance of STBCs: from COD (e.g., Alamouti code) can be simply obtained from existing analytical expressions for receive diversity with the same diversity order by appropriately scaling the SNR, this can not be done for STBCs from GCOD (because of the unequal norms of the column vectors). Our contribution in this paper is that we derive analytical expressions for the BER performance of any STBC from GCOD. Our BER analysis for the GCOD captures the performance of STBCs from COD as special cases. We validate our results with two STBCs from GCOD reported by Su and Xia in [1], for 5 and 6 transmit antennas (G(5) and G(6) in [1]) with rates 7/11 and 3/5, respectively.

On the maximal rate of (n+1) x n and (n+2) x n complex orthogonal designs

For p x n complex orthogonal designs in k variables, where p is the number of channels uses and n is the number of transmit antennas, the maximal rate L of the design is asymptotically half as n increases. But, for such maximal rate codes, the decoding delay p increases exponentially. To control the delay, if we put the restriction that p = n, i.e., consider only the square designs, then, the rate decreases exponentially as n increases. This necessitates the study of the maximal rate of the designs with restrictions of the form p = n+1, p = n+2, p = n+3 etc. In this paper, we study the maximal rate of complex orthogonal designs with the restrictions p = n+1 and p = n+2. We derive upper and lower bounds for the maximal rate for p = n+1 and p = n+2. Also for the case of p = n+1, we show that if the orthogonal design admit only the variables, their negatives and multiples of these by root-1 and zeros as the entries of the matrix (other complex linear combinations are not allowed), then the maximal rate always equals the lower bound.

A Novel Construction of Complex Orthogonal Designs with Maximal Rate and Low-PAPR

Space-time block codes based on orthogonal designs are used for wireless communications with multiple transmit antennas which can achieve full transmit diversity and have low decoding complexity. However, the rate of the square real/complex orthogonal designs tends to zero with increase in number of antennas, while it is possible to have a rate-1 real orthogonal design (ROD) for any number of antennas.In case of complex orthogonal designs (CODs), rate-1 codes exist only for 1 and 2 antennas. In general, For a transmit antennas, the maximal rate of a COD is 1/2 + l/n or 1/2 + 1/n+1 for n even or odd respectively. In this paper, we present a simple construction for maximal-rate CODs for any number of antennas from square CODs which resembles the construction of rate-1 RODs from square RODs. These designs are shown to be amenable for construction of a class of generalized CODs (called Coordinate-Interleaved Scaled CODs) with low peak-to-average power ratio (PAPR) having the same parameters as the maximal-rate codes. Simulation results indicate that these codes perform better than the existing maximal rate codes under peak power constraint while performing the same under average power constraint.

Training-Symbol Embedded, High-Rate Complex Orthogonal Designs for Relay Networks

Distributed Space-Time Block Codes (DSTBCs) from Complex Orthogonal Designs (CODs) (both square and non-square CODs other than the Alamouti design) are known to lose their single-symbol ML decodable (SSD) property when used in two-hop wireless relay networks using the amplify and forward protocol. For such a network, a new class of high rate, training-symbol embedded (TSE) SSD DSTBCs are proposed from TSE-CODs. The constructed codes include the training symbols within the structure of the code which is shown to be the key point to obtain high rate along with the SSD property. TSE-CODs are shown to offer full-diversity for arbitrary complex constellations. Non-square TSE-CODs are shown to provide better rates (in symbols per channel use) compared to the known SSD DSTBCs for relay networks when the number of relays is less than 10. Importantly, the proposed DSTBCs do not contain zeros in their codewords and as a result, antennas of the relay nodes do not undergo a sequence of switch on and off transitions within every codeword use. Hence, the proposed DSTBCs eliminate the antenna switching problem.

Computing Fractal Dimension of Signals using Multiresolution Box-counting Method

In this paper, we have developed a method to compute fractal dimension (FD) of discrete time signals, in the time domain, by modifying the box-counting method. The size of the box is dependent on the sampling frequency of the signal. The number of boxes required to completely cover the signal are obtained at multiple time resolutions. The time resolutions are made coarse by decimating the signal. The loglog plot of total number of boxes required to cover the curve versus size of the box used appears to be a straight line, whose slope is taken as an estimate of FD of the signal. The results are provided to demonstrate the performance of the proposed method using parametric fractal signals. The estimation accuracy of the method is compared with that of Katz, Sevcik, and Higuchi methods. In ddition, some properties of the FD are discussed.

Symmetrizing a Hessenberg matrix: Designs for VLSI parallel processor arrays

A symmetrizer of a nonsymmetric matrix A is the symmetric matrix X that satisfies the equation XA = A(t)X, where t indicates the transpose. A symmetrizer is useful in converting a nonsymmetric eigenvalue problem into a symmetric one which is relatively easy to solve and finds applications in stability problems in control theory and in the study of general matrices. Three designs based on VLSI parallel processor arrays are presented to compute a symmetrizer of a lower Hessenberg matrix. Their scope is discussed. The first one is the Leiserson systolic design while the remaining two, viz., the double pipe design and the fitted diagonal design are the derived versions of the first design with improved performance.

Precoder Designs for MIMO Broadcast Channels with Imperfect CSI

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Finding a Box Representation for a Graph in $O(n^2\Delta^2\ln n)$ time

An axis-parallel box in $b$-dimensional space is a Cartesian product $R_1 \times R_2 \times \cdots \times R_b$ where $R_i$ (for $1 \leq i \leq b$) is a closed interval of the form $[a_i, b_i]$ on the real line. For a graph $G$, its boxicity is the minimum dimension $b$, such that $G$ is representable as the intersection graph of (axis-parallel) boxes in $b$-dimensional space. The concept of boxicity finds application in various areas of research like ecology, operation research etc. Chandran, Francis and Sivadasan gave an $O(\Delta n^2 \ln^2 n)$ randomized algorithm to construct a box representation for any graph $G$ on $n$ vertices in $\lceil (\Delta + 2)\ln n \rceil$ dimensions, where $\Delta$ is the maximum degree of the graph. They also came up with a deterministic algorithm that runs in $O(n^4 \Delta )$ time. Here, we present an $O(n^2 \Delta^2 \ln n)$ deterministic algorithm that constructs the box representation for any graph in $\lceil (\Delta + 2)\ln n \rceil$ dimensions.

A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

Channel Precoding for STBCs from Generalized Pseudo Orthogonal Designs

Statistical information about the wireless channel can be used at the transmitter side to enhance the performance of MIMO systems. This paper addresses how the concept of channel precoding can be used to enhance the performance of STBCs from Generalized Pseudo Orthogonal Designs which were first introduced by Zhu and Jafarkhani. Such designs include some important classes of STBCs that are directly derivable from Quasi-Orthogonal Designs and Co-ordinate Interleaved Orthogonal Designs.

“Post silicon debug of SOC designs”

Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces

An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.

Features of a unique intronless cluster of class I small heat shock protein genes in tandem with box C/D snoRNA genes on chromosome 6 in tomato (Solanum lycopersicum)

Physical clustering of genes has been shown in plants; however, little is known about gene clusters that have different functions, particularly those expressed in the tomato fruit. A class I 17.6 small heat shock protein (Sl17.6 shsp) gene was cloned and used as a probe to screen a tomato (Solanum lycopersicum) genomic library. An 8.3-kb genomic fragment was isolated and its DNA sequence determined. Analysis of the genomic fragment identified intronless open reading frames of three class I shsp genes (Sl17.6, Sl20.0, and Sl20.1), the Sl17.6 gene flanked by Sl20.1 and Sl20.0, with complete 5' and 3' UTRs. Upstream of the Sl20.0 shsp, and within the shsp gene cluster, resides a box C/D snoRNA cluster made of SlsnoR12.1 and SlU24a. Characteristic C and D, and C' and D', boxes are conserved in SlsnoR12.1 and SlU24a while the upstream flanking region of SlsnoR12.1 carries TATA box 1, homol-E and homol-D box-like cis sequences, TM6 promoter, and an uncharacterized tomato EST. Molecular phylogenetic analysis revealed that this particular arrangement of shsps is conserved in tomato genome but is distinct from other species. The intronless genomic sequence is decorated with cis elements previously shown to be responsive to cues from plant hormones, dehydration, cold, heat, and MYC/MYB and WRKY71 transcription factors. Chromosomal mapping localized the tomato genomic sequence on the short arm of chromosome 6 in the introgression line (IL) 6-3. Quantitative polymerase chain reaction analysis of gene cluster members revealed differential expression during ripening of tomato fruit, and relatively different abundances in other plant parts.

Low-Delay, High-Rate Nonsquare Complex Orthogonal Designs

The maximal rate of a nonsquare complex orthogonal design for transmit antennas is 1/2 + 1/n if is even and 1/2 + 1/n+1 if is odd and the codes have been constructed for all by Liang (2003) and Lu et al. (2005) to achieve this rate. A lower bound on the decoding delay of maximal-rate complex orthogonal designs has been obtained by Adams et al. (2007) and it is observed that Liang's construction achieves the bound on delay for equal to 1 and 3 modulo 4 while Lu et al.'s construction achieves the bound for n = 0, 1, 3 mod 4. For n = 2 mod 4, Adams et al. (2010) have shown that the minimal decoding delay is twice the lower bound, in which case, both Liang's and Lu et al.'s construction achieve the minimum decoding delay. For large value of, it is observed that the rate is close to half and the decoding delay is very large. A class of rate-1/2 codes with low decoding delay for all has been constructed by Tarokh et al. (1999). In this paper, another class of rate-1/2 codes is constructed for all in which case the decoding delay is half the decoding delay of the rate-1/2 codes given by Tarokh et al. This is achieved by giving first a general construction of square real orthogonal designs which includes as special cases the well-known constructions of Adams, Lax, and Phillips and the construction of Geramita and Pullman, and then making use of it to obtain the desired rate-1/2 codes. For the case of nine transmit antennas, the proposed rate-1/2 code is shown to be of minimal delay. The proposed construction results in designs with zero entries which may have high peak-to-average power ratio and it is shown that by appropriate postmultiplication, a design with no zero entry can be obtained with no change in the code parameters.