Fin-Enabled-Area-Scaled Tunnel FET

While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements.

Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA

Support vector machines (SVM) are a popular class of supervised models in machine learning. The associated compute intensive learning algorithm limits their use in real-time applications. This paper presents a fully scalable architecture of a coprocessor, which can compute multiple rows of the kernel matrix in parallel. Further, we propose an extended variant of the popular decomposition technique, sequential minimal optimization, which we call hybrid working set (HWS) algorithm, to effectively utilize the benefits of cached kernel columns and the parallel computational power of the coprocessor. The coprocessor is implemented on Xilinx Virtex 7 field-programmable gate array-based VC707 board and achieves a speedup of upto 25x for kernel computation over single threaded computation on Intel Core i5. An application speedup of upto 15x over software implementation of LIBSVM and speedup of upto 23x over SVMLight is achieved using the HWS algorithm in unison with the coprocessor. The reduction in the number of iterations and sensitivity of the optimization time to variation in cache size using the HWS algorithm are also shown.

Estimation of Power Input to Complex Dielectric Barrier Discharge Reactor Geometries used in NOx Cleaning

Studies were carried out to estimate the power input to Dielectric Barrier Discharge (DBD) reactors powered by AC high voltage in the context of their application in non-thermal plasma cleaning of exhaust gases. Power input to the reactors was determined both theoretically and experimentally. Four different reactor geometries energized with 50 Hz and 1.5 kHz AC excitation were considered for the study. The theoretically estimated power using Manley's equation was found to agree with the experimental results. Results show that the analytically computed capacitance, without including the electrode edge effects, gives sufficiently good results that are matching with the measured values. For complex geometries where analytical calculation of capacitance is often difficult, a novel method of estimating the reactor capacitance, and hence the power input to the reactor, was introduced in this paper. The predicted results were validated with experiments.

Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device

In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

A Simple Hysteretic Energy Harvesting Method for Nonneutral AC Switches in Load Automation

This paper presents a simple hysteretic method to obtain the energy required to operate the gate-drive, sensors, and other circuits within nonneutral ac switches intended for use in load automated buildings. The proposed method features a switch-mode low part-count self-powered MOSFET ac switch that achieves efficiency and load current THD figures comparable to those of an externally gate-driven switch built using similar MOSFETS. The fundamental operation of the method is explained in detail, followed by the modifications required for practical implementation. Certain design rules that allow the method to accommodate a wide range of single-phase loads from 10 VA to 1 kVA are discussed, along with an efficiency enhancement feature based on inherent MOSFET characteristics. The limitations and side effects of the method are also mentioned according to their levels of severity. Finally, experimental results obtained using a prototype sensor switch are presented, along with a performance comparison of the prototype with an externally gate-driven MOSFET switch.

Accelerating method of moments based package-board 3D parasitic extraction using FPGA

In this article, a Field Programmable Gate Array (FPGA)-based hardware accelerator for 3D electromagnetic extraction, using Method of Moments (MoM) is presented. As the number of nets or ports in a system increases, leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products presents a time bottleneck in a linear-complexity fast solver framework. In this work, an FPGA-based hardware implementation is proposed toward a two-level parallelization scheme: (i) matrix level parallelization for single RHS and (ii) pipelining for multiple-RHS. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple nets in a Ball Grid Array (BGA) package. The acceleration is shown to be linearly scalable with FPGA resources and speed-ups over 10x against equivalent software implementation on a 2.4GHz Intel Core i5 processor is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board with the implemented design operating at 200MHz clock frequency. (c) 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:776-783, 2016

Corona Degradation of the Polymer Insulator Samples under Different Fog Conditions

Corona discharges resulting from the metal parts of insulators and the line hardware affect the long term performance of the polymeric insulators used for outdoor application and can lead to its eventual failure. The authors previous work, involved in developing a new methodology to evaluate the performance of polymeric shed materials subjected to corona stresses in the presence of natural fog condition, results revealed more surface hydroxylation thereby resulting in more loss of hydropobhicity. With the increase in industrialization, there is an increase in acidic component of the rain as well as the fog (moisture). The present work, reports the effect of acid fog on the corona performance of the polymeric insulators for both AC and DC excitation, interesting results are obtained. A comparison of the experimental investigations revealed that the acidic fog has more effect than that of the normal fog. This fact has been confirmed by physico-chemical analysis like the scanning electron microscopy (SEM), Fourier transform infrared spectroscopy (FTIR), x-ray photoelectron spectroscopy (XPS) and contact angle measurement. The effect of DC corona is found to be lesser in comparison with the AC; however the hydroxylation induced by the DC corona under the presence of fog is similar with that of AC excitation.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

Enhancing photoresponsivity using MoTe2-graphene vertical heterostructures

MoTe2 with a narrow band-gap of similar to 1.1 eV is a promising candidate for optoelectronic applications, especially for the near-infrared photo detection. However, the photo responsivity of few layers MoTe2 is very small (<1mAW(-1)). In this work, we show that a few layer MoTe2-graphene vertical heterostructures have a much larger photo responsivity of similar to 20mAW(-1). The trans-conductance measurements with back gate voltage show on-off ratio of the vertical transistor to be similar to(0.5-1) x 10(5). The rectification nature of the source-drain current with the back gate voltage reveals the presence of a stronger Schottky barrier at the MoTe2-metal contact as compared to the MoTe2-graphene interface. In order to quantify the barrier height, it is essential to measure the work function of a few layers MoTe2, not known so far. We demonstrate a method to determine the work function by measuring the photo-response of the vertical transistor as a function of the Schottky barrier height at the MoTe2-graphene interface tuned by electrolytic top gating. (C) 2016 AIP Publishing LLC.