Methanol oxidation on carbon-supported Pt---Sn electrodes in silicotungstic acid

Electro-oxidation of methanol was studied on carbon-supported Pt-Sn/C electrodes in silcotungstic acid (SiWA) at various concentrations. The porous-carbon electrodes employing Pt-Sn/C catalyst have been characterized using chemical analyses, X-ray powder diffraction (XRD) and X-ray photoelectron spectroscopy (XPS) in conjunction with electrochemistry. The presence of Pt-Sn and Pt3Sn alloys along with Pt and SnO2 phases in the catalyst were identified by XRD. XPS analysis showed a lower amount of PtO species in the Pt-Sn/C catalyst with respect to the corresponding Pt/C sample. From the steady-state galvanostatic polarization data on Pt-Sn/C electrodes in SiWA, it is inferred that a one-electron process is the rate determining step. The performance of the electrodes in 0.084 M SiWA was better than in 2.5 M H2SO4 under similar conditions up to load currents of about 100 mA cm-2 indicating the promoting behaviour of the electrolyte. At currents larger than 100 mA cm-2, the performance of the electrodes in 0.084 SiWA was poorer than that in 2.5M H2SO4 mainly due to the dominance of mass polarization in the former owing to the large size of Keggin units associated with the structure of SiWA. This aspect was supported by cyclic voltammetry and ac impedance studies on Pt-Sn/C electrodes. Simulation of the electrochemical impedance response for the oxidation of methanol in SiWA was carried out using the equivalent electrical circuit model.

Dynamic analysis of voltage instability in AC-DC systems

This paper presents the analysis and study of voltage collapse at any converter bus in A C-DC systems considering the dynamics of DC system. The problem of voltage instability is acute when HVDC links are connected to weak AC systems, the strength determined by short circuit ratio (SCR) at the converter bus. The converter control strategies are important in determining voltage instability. Small signal analysis is used to identify critical modes and evaluate the effect of AC system strength and control parameters. A sample two-terminal DC system is studied and the results compared with those obtained from static analysis. Also, the results obtained from small signal analysis are validated with nonlinear simulation.

Effect of TiO2 electrode thickness on photovoltaic properties of dye sensitized solar cell based on randomly oriented Titania nanotubes

Anatase titania nanotubes (TNTs) have been synthesized from P25 TiO2 powder by alkali hydrothermal method followed by post annealing. The microstructure analysis by X-ray diffraction (XRD), transmission electron microscopy (TEM) and scanning electron microscopy (SEM) revealed the formation of anatase nanotubes with a diameter of 9-10 nm. These NTs are used to make photo anode in dye-sensitized solar cells (DSSCs). Layer by layer deposition with curing of each layer at 350 C is employed to realize films of desired thickness. The performance of these cells is studied using photovoltaic measurements. Electrochemical impedance spectroscopy (EIS) is used to quantitatively analyze the effect of thickness on the performance of these cells. These studies revealed that the thickness of TiO2 has a pronounced impact on the cell performance and the optimum thickness lies in the range of 10-14 mu m. In comparison to dye solar cells made of P25, TNTs based cells exhibit an improved open circuit voltage and fill factor (FF) due to an increased electron lifetime, as revealed by EIS analysis. (C) 2011 Elsevier B.V. All rights reserved.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

On the performance of stabilized ?-nickel hydroxide as a nickel-positive electrode in alkaline storage batteries

The internal resistance of a stabilized alpha-nickel hydroxide electrode is found to be lower than that of a beta-nickel hydroxide electrode as shown from studies of the open-circuit potential-time transients at all states-of-charge. Nevertheless, the self-discharge rates of the former is higher. Gasometric studies reveal that the charging efficiency of the alpha-nickel hydroxide electrode is higher than that of the beta-nickel hydroxide electrode.

Link failure detection for maintaining session continuity in packet data networks

A link failure in the path of a virtual circuit in a packet data network will lead to premature disconnection of the circuit by the end-points. A soft failure will result in degraded throughput over the virtual circuit. If these failures can be detected quickly and reliably, then appropriate rerouteing strategies can automatically reroute the virtual circuits that use the failed facility. In this paper, we develop a methodology for analysing and designing failure detection schemes for digital facilities. Based on errored second data, we develop a Markov model for the error and failure behaviour of a T1 trunk. The performance of a detection scheme is characterized by its false alarm probability and the detection delay. Using the Markov model, we analyse the performance of detection schemes that use physical layer or link layer information. The schemes basically rely upon detecting the occurrence of severely errored seconds (SESs). A failure is declared when a counter, that is driven by the occurrence of SESs, reaches a certain threshold.For hard failures, the design problem reduces to a proper choice;of the threshold at which failure is declared, and on the connection reattempt parameters of the virtual circuit end-point session recovery procedures. For soft failures, the performance of a detection scheme depends, in addition, on how long and how frequent the error bursts are in a given failure mode. We also propose and analyse a novel Level 2 detection scheme that relies only upon anomalies observable at Level 2, i.e. CRC failures and idle-fill flag errors. Our results suggest that Level 2 schemes that perform as well as Level 1 schemes are possible.

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface.

Analysis, Design, Modeling, and Implementation of an Active Clamp HF Link Converter

This paper deals with the system oriented analysis, design, modeling, and implementation of active clamp HF link three phase converter. The main advantage of the topology is reduced size, weight, and cost of the isolation transformer. However, violation of basic power conversion rules due to presence of the leakage inductance in the HF transformer causes over voltage stresses across the cycloconverter devices. It makes use of the snubber circuit necessary in such topologies. The conventional RCD snubbers are dissipative in nature and hence inefficient. The efficiency of the system is greatly improved by using regenerative snubber or active clamp circuit. It consists of an active switching device with an anti-parallel diode and one capacitor to absorb the energy stored in the leakage inductance of the isolation transformer and to regenerate the same without affecting circuit performance. The turn on instant and duration of the active device are selected such that it requires simple commutation requirements. The time domain expressions for circuit dynamics, design criteria of the snubber capacitor with two conflicting constrains (over voltage stress across the devices and the resonating current duration), the simulation results based on generalized circuit model and the experimental results based on laboratory prototype are presented.

Antiferroelectric lead zirconate thin films by pulsed laser ablation

Lead Zirconate (PbZrO3) thin films were deposited by pulsed laser ablation method. Pseudocubic (110) oriented in-situ films were grown at low pressure. The field enforced anti-ferroelectric (AFE) to ferroelectric (FE) phase transformation behaviour was investigated by means of a modified Sawyer Tower circuit as well as capacitance versus applied voltage measurements. The maximum polarisation obtained was 36 mu C cm(-2) and the critical field to induce ferroelectric state and to reverse the antiferroelectric slates were 65 and 90 kV cm(-1) respectively. The dielectric properties were investigated as a function of frequency and temperature. The dielectric constant of the AFE lead zirconate thin him was 190 at 100 kHz which is more than the bulk ceramic value (120) with a dissipation factor of less than 0.07. The polarisation switching kinetics of the antiferroelectric PbZrO3 thin films showed that the switching time to be around 275 ns between antipolar state to polar states. (C) 1999 Elsevier Science S.A. All rights reserved.

Sensing of delaminations in composite laminates using embedded magnetostrictive particle layers

This is an exploratory study to illustrate the feasibility of detecting delamination type of damage in polymeric laminates with one layer of magnetostrictive particles. One such beam encircled with excitation and sensing coils is used for this study. The change in stress gradient of the magnetostrictive layer in the vicinity of delamination shows up as a change in induced voltage in the sensing coil, and therefore provides a means to sense the presence of delamination. Recognizing the constitutive behavior of the Terfenol-D material is highly nonlinear, analytical expressions for the constitutive relations are developed by using curve fitting techniques to the experimental data. Analytical expressions that relate the applied excitation field with the stress and magnetic flux densities induced in the magnetostrictive layer are developed. Numerical methods are used to find the relative change in the induced voltage in the sensing coil due to the presence of delamination. A typical example of unidirectional laminate, with embedded delaminations, is used for the simulation purposes. This exploratory study illustrates that the open-circuit voltage induced in the sensing coil changes significantly (as large of 68 millivolts) with the occurrence of delamination. This feature can be exploited for device off-line inspection techniques and/or linking monitoring procedures for practical applications.

Capacitive-Resistive Transients in terms of field quantities

Capacitive-resistive transients in extended media are discussed in tenns of electric field quantities. Obviously, in rhese problems, the contribution of the magnetlc field to the electric field is deemed negligible. For a simple lllusfratlve example, the field solution is compared with the circuit-theoretical resuit for the voltage and current. An algorithm for solving such transients in space and time doman with the help of a Laplace solver is presented. Any other Laplace solver can also be used far this purpose. Its applicability is demonstrated with three examples, one of which is chosen to have a circuit-theoretical solution.

Dodecagonal space vector diagram using cascaded H-Bridge inverters

This paper proposes the development of dodecagonal (12-sided) space vector diagrams from cascaded H-Bridge inverters. As already reported in literatures, dodecagonal space vector diagrams have many advantages over conventional hexagonal ones. Some of them include the absence of 6n±1, (n=odd) harmonics from the phase voltage, and the extension of the linear modulation range. In this paper, a new power circuit is proposed for generating multiple dodecagons in the space vector plane. It consists of two cascaded H-Bridge cells fed from asymmetric dc voltage sources. It is shown that, with proper PWM timing calculation and placement of active and zero vectors, a very high quality of sine-wave can be produced. At the same time, the switching frequency of individual cells can be reduced substantially. Detailed PWM analysis, one design example and an elaborate simulation study is presented to support the proposed idea.

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Electrical characterization of Ba(Zr0.1Ti0.9)O-3 thin films grown by pulsed laser ablation technique

In situ annealed thin films of ferroelectric Ba(Zr0.1Ti0.9)O-3 were deposited on platinum substrates by pulsed laser ablation technique. The as grown films were polycrystalline in nature without the evidence of any secondary phases. The polarization hysteresis loop confirmed the ferroelectricity, which was also cross-checked with the capacitance-voltage characteristics. The remnant polarization was about 5.9 muC cm(-2) at room temperature and the coercive field was 45 kV. There was a slight asymmetry in the hysteresis for different polarities, which was thought to be due to the work function differences of different electrodes. The dielectric constant was about 452 and was found to exhibit low frequency dispersion that increased with frequency, This was related to the space-charge polarization. The complex impedance was plotted and this exhibited a semicircular trace, and indicated an equivalent parallel R - C circuit within the sample. This was attributed to the grain response. The DC leakage current-voltage plot was consistent with the space-charge limited conduction theory, but showed some deviation, which was explained by assuming a Poole-Frenkel type conduction to be superimposed on to the usual space-charge controlled current. (C) 2002 Elsevier Science B.V. All rights reserved.

Starting scheme for load commutated inverter-fed wound field synchronous machine using an auxiliary low-power voltage source inverter

Conventional thyristor-based load commutated inverter (LCI)-fed wound field synchronous machine operates only above a minimum speed that is necessary to develop enough back emf to ensure commutation. The drive is started and brought up to a speed of around 10-15% by a complex `dc link current pulsing' technique. During this process, the drive have problems such as pulsating torque, insufficient average starting torque, longer starting time, etc. In this regard a simple starting and low-speed operation scheme, by employing an auxiliary low-power voltage source inverter (VSI) between the LCI and the machine terminals, is presented in this study. The drive is started and brought up to a low speed of around 15% using the VSI alone with field oriented control. The complete control is then smoothly and dynamically transferred to the conventional LCI control. After the control transfer, the VSI is turned off and physically disconnected from the main circuit. The advantages of this scheme are smooth starting, complete control of torque and flux at starting and low speeds, less starting time, stable operation, etc. The voltage rating of the required VSI is very low of the order of 10-15%, whereas the current rating is dependent on the starting torque requirement of the load. The experimental results from a 15.8 hp LCI-fed wound field synchronous machine are given to demonstrate the scheme.