STM verification of the reduction of the Young's modulus of CdS nanoparticles at smaller sizes

We demonstrate the first STM evaluation of the Young's modulus (E) of nanoparticles (NPs) of different sizes. The sample deformation induced by tip-sample interaction has been determined using current-distance (I-Z) spectroscopy. As a result of tip-sample interaction, and the induced surface deformations, the I-z curves deviates from pure exponential dependence. Normally, in order to analyze the deformation quantitatively, the tip radius must be known. We show, that this necessity is eliminated by measuring the deformation on a substrate with a known Young's modulus (Au(111)) and estimating the tip radius, and afterwards, using the same tip (with a known radius) to measure the (unknown) Young's modulus of another sample (nanoparticles of CdS). The Young's modulus values found for 3 NP's samples of average diameters of 3.7, 6 and 7.5 nm, were E similar to 73%, 78% and 88% of the bulk value, respectively. These results are in a good agreement with the theoretically predicted reduction of the Young's modulus due to the changes in hydrostatic stresses which resulted from surface tension in nanoparticles with different sizes. Our calculation using third order elastic constants gives a reduction of E which scales linearly with 1/r (r is the NP's radius). This demonstrates the applicability of scanning tunneling spectroscopy for local mechanical characterization of nanoobjects. The method does not include a direct measurement of the tip-sample force but is rather based on the study of the relative elastic response. (C) 2014 Elsevier B.V. All rights reserved.

Microstructure dependent elastic modulus variation in NiTi shape memory alloy

Modulus variation of NiTi shape memory alloy has been investigated at microstructural level through nano dynamical mechanical analysis and compared with bulk experimental measurements. The differences between the modulus values at the macro and micro level as well as within the micro level are discussed and the corresponding variations have been explained based on the crystal structure, orientation and misorientation. The experimental results confirm a higher modulus value for the martensite phase that is in agreement with the theoretical predictions. (C) 2015 Elsevier B. V. All rights reserved.

Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems

This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.

Effects of Interface Treatment on the Fatigue Behavior of Shape Memory Alloy Reinforced Polymer Composites

Interfacial properties of Shape Memory Alloy (SMA) reinforced polymer matrix composites can be enhanced by improving the interfacial bonding. This paper focuses on studying the interfacial stresses developed in the SMA-epoxy interface due to various laser shot penning conditions. Fiber-pull test-setup is designed to understand the role of mechanical bias stress cycling and thermal actuation cycling. Phase transformation is tracked over mechanical and thermal fatigue cycles. A micromechanics based model developed earlier based on shear lag in SMA and energy based consistent homogenization is extended here to incorporate the stress-temperature phase diagram parameters for modeling fatigue.

Co-Exploration of NLA Kernels and Specification of Compute Elements in Distributed Memory CGRAs

Coarse Grained Reconfigurable Architectures (CGRA) are emerging as embedded application processing units in computing platforms for Exascale computing. Such CGRAs are distributed memory multi- core compute elements on a chip that communicate over a Network-on-chip (NoC). Numerical Linear Algebra (NLA) kernels are key to several high performance computing applications. In this paper we propose a systematic methodology to obtain the specification of Compute Elements (CE) for such CGRAs. We analyze block Matrix Multiplication and block LU Decomposition algorithms in the context of a CGRA, and obtain theoretical bounds on communication requirements, and memory sizes for a CE. Support for high performance custom computations common to NLA kernels are met through custom function units (CFUs) in the CEs. We present results to justify the merits of such CFUs.

Growth and characteristics of amorphous Sb2Se3 thin films of various thicknesses for memory switching applications

Thin films of different thicknesses in the range of 200-720 nm have been deposited on glass substrates at room temperature using thermal evaporation technique. The structural investigations revealed that the as-deposited films are amorphous in nature. The surface roughness of the films shows an increasing trend at higher thickness of the films. The surface roughness of the films shows an increasing trend at higher thickness of the films. Interference fringes in the transmission spectra of these films suggest that the films are fairly smooth and uniform. The optical absorption in Sb2Se3 film is described using indirect transition and the variation in band gaps is explained on the basis of defects and disorders in the chalcogenide systems. Raman spectrum confirms the increase of orderliness with film thickness. From the I-V characteristics, a memory type switching is observed whose threshold voltage increases with film thickness. (C) 2015 Elsevier B.V. All rights reserved.

An efficient design of serial and parallel memory using Quantum dot cellular automata

Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10nm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%.These circuits are the building block of nano processors and provide us to understand the nano devices of the future.

All Inorganic Spin-Coated Nanoparticle-Based Capacitive Memory Devices

We demonstrate all inorganic, robust, cost-effective, spin-coated, two-terminal capacitive memory metal-oxide nanoparticle-oxide-semiconductor devices with cadmium telluride nanoparticles sandwiched between aluminum oxide phosphate layers to form the dielectric memory stack. Using a novel high-speed circuit to decouple reading and writing, experimentally measured memory windows, programming voltages, retention times, and endurance are comparable with or better than the two-terminal memory devices realized using other fabrication techniques.