In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Magnetically tunable nonlinear current-voltage characteristics in oxygen deficient manganite perovskites

(La0.667Ca0.333Mn1-xMO3-delta)-O-x (M = Mg, Li or Re) exhibit insulating behaviour and nonlinear current-voltage (J-E) relationship with voltage-limiting characteristics at temperatures below the ferromagnetic transition (T-c). The high current region is set in at field strengths <60 V/cm. Nonlinearity exponent, alpha in the relation J = kE(alpha) increases inversely with temperature. In presence of an external magnetic field, the J-E curves show higher current density at lower field strengths. Microstructural studies indicate that there is no segregation of secondary phases in the grain boundary regions. There is remarkable changes in p(T) as well as J-E curves with the grain size. Annealing studies in lower p(O2) atmospheres indicate that there is significant out-diffusion of oxygen ions through the grain boundary layer (GBL) regions creating oxygen vacancies in the GBL regions. The concentration of Mn4+ ions is lowered at the GBL due to oxygen vacancies, reducing the probability of hopping and resulting in insulating behaviour. Therefore an insulating barrier is introduced between two conducting grains and the carrier motion between the grains is inhibited. Thus below T-c, where sufficient increase in resistivity is observed the conduction may be arising as a result of spin dependent tunneling across the barrier. External electric field lowers the barrier height and establishes carrier transport across the barrier. Above certain field strength, barrier height diminishes significantly and thereby allowing large number of carriers for conduction, giving rise to highly nonlinear conductivity. (C) 2002 Elsevier Science B.V. All rights reserved.

Starting scheme for load commutated inverter-fed wound field synchronous machine using an auxiliary low-power voltage source inverter

Conventional thyristor-based load commutated inverter (LCI)-fed wound field synchronous machine operates only above a minimum speed that is necessary to develop enough back emf to ensure commutation. The drive is started and brought up to a speed of around 10-15% by a complex `dc link current pulsing' technique. During this process, the drive have problems such as pulsating torque, insufficient average starting torque, longer starting time, etc. In this regard a simple starting and low-speed operation scheme, by employing an auxiliary low-power voltage source inverter (VSI) between the LCI and the machine terminals, is presented in this study. The drive is started and brought up to a low speed of around 15% using the VSI alone with field oriented control. The complete control is then smoothly and dynamically transferred to the conventional LCI control. After the control transfer, the VSI is turned off and physically disconnected from the main circuit. The advantages of this scheme are smooth starting, complete control of torque and flux at starting and low speeds, less starting time, stable operation, etc. The voltage rating of the required VSI is very low of the order of 10-15%, whereas the current rating is dependent on the starting torque requirement of the load. The experimental results from a 15.8 hp LCI-fed wound field synchronous machine are given to demonstrate the scheme.

A Novel VSI- and CSI-Fed Dual Stator Induction Motor Drive Topology for Medium-Voltage Drive Applications

A new configuration is proposed for high-power induction motor drives. The induction machine is provided with two three-phase stator windings with their axes in line. One winding is designed for higher voltage and is meant to handle the main (active) power. The second winding is designed for lower voltage and is meant to carry the excitation (reactive) power. The excitation winding is powered by an insulated-gate-bipolar-transistor-based voltage source inverter with an output filter. The power winding is fed by a load-commutated current source inverter. The commutation of thyristors in the load-commutated inverter (LCI) is achieved by injecting the required leading reactive power from the excitation inverter. The MMF harmonics due to the LCI current are also cancelled out by injecting a suitable compensating component from the excitation inverter, so that the electromagnetic torque of the machine is smooth. Results from a prototype drive are presented to demonstrate the concept.

An Investigation into the Dependence of the Arc Voltage on the Parameters of the Short-Circuit Current and the Design of the Vacuum Interrupter

The vacuum interrupter is extensively employed in the medium voltage switchgear for the interruption of the short-circuit current. The voltage across the arc during current interruption is termed as the arc voltage. The nature and magnitude of this arc voltage is indicative of the performance of the contacts and the vacuum interrupter as a whole. Also, the arc voltage depends on the parameters like the magnitude of short-circuit current, the arcing time, the point of opening of the contacts, the geometry and area of the contacts and the type of magnetic field. This paper investigates the dependency of the arc voltage on some of these parameters. The paper also discusses the usefulness of the arc voltage in diagnosing the performance of the contacts.

Conformational basis for substrate recognition and regulation of catalytic activity in Staphylococcus aureus nucleoside di-phosphate kinase

Nucleoside diphosphate kinases (NDK) are characterized by high catalytic turnover rates and diverse substrate specificity. These features make this enzyme an effective activator of a pro-drug an application that has been actively pursued for a variety of therapeutic strategies. The catalytic mechanism of this enzyme is governed by a conserved histidine that coordinates a magnesium ion at the active site. Despite substantial structural and biochemical information on NDK, the mechanistic feature of the phospho-transfer that leads to auto-phosphorylation remains unclear. While the role of the histidine residue is well documented, the other active site residues, in particular the conserved serine remains poorly characterized. Studies on some homologues suggest no role for the serine residue at the active site, while others suggest a crucial role for this serine in the regulation and quaternary association of this enzyme in some species. Here we report the biochemical features of the Staphylococcus aureus NDK and the mutant enzymes. We also describe the crystal structures of the apo-NDK, as a transition state mimic with vanadate and in complex with different nucleotide substrates. These structures formed the basis for molecular dynamics simulations to understand the broad substrate specificity of this enzyme and the role of active site residues in the phospho-transfer mechanism and oligomerization. Put together, these data suggest that concerted changes in the conformation of specific residues facilitate the stabilization of nucleotide complexes thereby enabling the steps involved in the ping-pong reaction mechanism without large changes to the overall structure of this enzyme. (C) 2011 Elsevier B.V. All rights reserved.

Cooperative Regulation of NOTCH1 Protein-Phosphatidylinositol 3-Kinase (PI3K) Signaling by NOD1, NOD2, and TLR2 Receptors Renders Enhanced Refractoriness to Transforming Growth Factor-beta (TGF-beta)- or Cytotoxic T-lymphocyte Antigen 4 (CTLA-4)-mediated Impairment of Human Dendritic Cell Maturation

Dendritic cells (DCs) as sentinels of the immune system are important for eliciting both primary and secondary immune responses to a plethora of microbial pathogens. Cooperative stimulation of a complex set of pattern-recognition receptors, including TLR2 and nucleotide-binding oligomerization domain (NOD)-like receptors on DCs, acts as a rate-limiting factor in determining the initiation and mounting of the robust immune response. It underscores the need for ``decoding'' these multiple receptor interactions. In this study, we demonstrate that TLR2 and NOD receptors cooperatively regulate functional maturation of human DCs. Intriguingly, synergistic stimulation of TLR2 and NOD receptors renders enhanced refractoriness to TGF-beta- or CTLA-4-mediated impairment of human DC maturation. Signaling perturbation data suggest that NOTCH1-PI3K signaling dynamics assume critical importance in TLR2- and NOD receptor-mediated surmounting of CTLA-4- and TGF-beta -suppressed maturation of human DCs. Interestingly, the NOTCH1-PI3K signaling axis holds the capacity to regulate DC functions by virtue of PKC delta-MAPK-dependent activation of NF-kappa B. This study provides mechanistic and functional insights into TLR2-and NOD receptor-mediated regulation of DC functions and unravels NOTCH1-PI3K as a signaling cohort for TLR2 and NOD receptors. These findings serve in building a conceptual foundation for the design of improved strategies for adjuvants and immunotherapies against infectious diseases.

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization

With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.

Energy Reduction in SRAM using Dynamic Voltage and Frequency Management

This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

Compiler-Directed Frequency and Voltage Scaling for a Multiple Clock Domain

Multiple Clock Domain processors provide an attractive solution to the increasingly challenging problems of clock distribution and power dissipation. They allow their chips to be partitioned into different clock domains, and each domain’s frequency (voltage) to be independently configured. This flexibility adds new dimensions to the Dynamic Voltage and Frequency Scaling problem, while providing better scope for saving energy and meeting performance demands. In this paper, we propose a compiler directed approach for MCD-DVFS. We build a formal petri net based program performance model, parameterized by settings of microarchitectural components and resource configurations, and integrate it with our compiler passes for frequency selection.Our model estimates the performance impact of a frequency setting, unlike the existing best techniques which rely on weaker indicators of domain performance such as queue occupancies(used by online methods) and slack manifestation for a particular frequency setting (software based methods).We evaluate our method with subsets of SPECFP2000,Mediabench and Mibench benchmarks. Our mean energy savings is 60.39% (versus 33.91% of the best software technique)in a memory constrained system for cache miss dominated benchmarks, and we meet the performance demands.Our ED2 improves by 22.11% (versus 18.34%) for other benchmarks. For a CPU with restricted frequency settings, our energy consumption is within 4.69% of the optimal.