Design Of Start-up Power Circuit For Control Power Supplies With Wide Input Voltage Variation

This paper presents the design of a start up power circuit for a control power supply (CPS) which feeds power to the sub-systems of High Power Converters (HPC). The sub-systems such as gate drive card, annunciation card, protection and delay card etc; needs to be provided power for the operation of a HPC. The control power supply (CPS) is designed to operate over a wide range of input voltage from 90Vac to 270Vac. The CPS output supplies power at a desired voltage of Vout =24V to the auxiliary sub-systems of the HPC. During the starting, the power supply to the control circuitry of CPS in turn, is obtained using a separate start-up power supply. This paper discusses the various design issues of the start-up power circuit to ensure that start-up and shut down of the CPS occurs reliably. The CPS also maintains the power factor close to unity and low total harmonic distortion in input current. The paper also provides design details of gate drive circuits employed for the CPS as well as the design of on-board power supply for the CPS. Index terms: control power supply, start-up power supply, DSFC, pre-regulator

Comparative Evaluation of Switching and Average Models of a DC-DC Boost Converter for Real-Time Simulation

This paper presents a comparative evaluation of the average and switching models of a dc-dc boost converter from the point of view of real-time simulation. Both the models are used to simulate the converter in real-time on a Field Programmable Gate Array (FPGA) platform. The converter is considered to function over a wide range of operating conditions, and could do transition between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). While the average model is known to be computationally efficient from the perspective of off-line simulation, the same is shown here to consume more logical resources than the switching model for real-time simulation of the dc-dc converter. Further, evaluation of the boundary condition between CCM and DCM is found to be the main reason for the increased consumption of resources by the average model.

Optically active heterostructures of graphene and ultrathin MoS2

Here we present the fabrication and characterization of a new class of hybrid devices where the constituents are graphene and ultrathin molybdenum di-sulphide (MoS2). This device is one of the simplest member of a family of hybrids where the desirable electrical characteristics of graphene such as high mobility are combined with optical activity of semiconductors. We find that in the presence of an optically active substrate, considerable photoconductivity is induced in graphene which is persistent up to a time scale of at least several hours. This photo induced memory can be erased by the application of a suitable gate voltage pulse. This memory operation is stable for many cycles. We present a theoretical model based on localized states in MoS2 which explains the data. (C) 2013 Elsevier Ltd. All rights reserved.

Type IA topoisomerase inhibition by clamp closure

Bacterial DNA topoisomerase I (topoI) catalyzes relaxation of negatively supercoiled DNA. The enzyme alters DNA topology through protein-operated DNA gate, switching between open and closed conformations during its reaction. We describe the mechanism of inhibition of Mycobacterium smegmatis and Mycobacterium tuberculosis topoI by monoclonal antibodies (mAbs) that bind with high affinity and inhibit at 10-50 nM concentration. Unlike other inhibitors of topoisomerases, the mAbs inhibited several steps of relaxation reaction, namely DNA binding, cleavage, strand passage, and enzyme-DNA dissociation. The enhanced religation of the cleaved DNA in presence of the mAb indicated closing of the enzyme DNA gate. The formation of enzyme-DNA heterocatenane in the presence of the mAbs as a result of closing the gate could be inferred by the salt resistance of the complex, visualized by atomic force microscopy and confirmed by fluorescence measurements. Locking the enzyme-DNA complex as a closed clamp restricted the movements of the DNA gate, affecting all of the major steps of the relaxation reaction. Enzyme trapped on DNA in closed clamp conformation formed roadblock for the elongating DNA polymerase. The unusual multistep inhibition of mycobacterial topoisomerases may facilitate lead molecule development, and the mAbs would also serve as valuable tools to probe the enzyme mechanism.

Suppression of air bubble in microfluidic channel using electro-acoustic excitation

A simple method to study the air bubble dynamics and to burst the air bubbles formed on the electrode– electrolyte interface in a parallel gate electrode fluidic channel is demonstrated. Upon application of a voltage across the electrodes,volume of water contained between them begins to electrolyzing depending on the conductivity, as well as it boils due to heating effect. This results in bubble formation within. These bubbles grow in radius with higher potential difference applied across the electrodes. As an approach towards removing these bubbles, an alternating current is applied at low potential difference of a 5 volts and high frequency at few megahertz. The alternating electric field had a heating effect on the bubbles where the energy input due to current heats up water and bursts the bubble. The bubbles of size up to 480μm were burst at 2500 V/m using this approach.

Large linear magnetoresistance in a GaAs/AlGaAs heterostructure

We report non-saturating linear magnetoresistance (MR) in a two-dimensional electron system (2DES) at a GaAs/AlGaAs heterointerface in the strongly insulating regime. We achieve this by driving the gate voltage below the pinch-off point of the device and operating it in the non-equilibrium regime with high source-drain bias. Remarkably, the magnitude of MR is as large as 500% per Tesla with respect to resistance at zero magnetic field, thus dwarfing most non-magnetic materials which exhibit this linearity. Its primary advantage over most other materials is that both linearity and the enormous magnitude are retained over a broad temperature range (0.3 K to 10 K), thus making it an attractive candidate for cryogenic sensor applications.

Electrostatic modulation of periodic potentials in a two-dimensional electron gas: from antidot lattice to quantum dot lattice

We use a dual gated device structure to introduce a gate-tuneable periodic potential in a GaAs/AlGaAs two dimensional electron gas (2DEG). Using only a suitable choice of gate voltages we can controllably alter the potential landscape of the bare 2DEG, inducing either a periodic array of antidots or quantum dots. Antidots are artificial scattering centers, and therefore allow for a study of electron dynamics. In particular, we show that the thermovoltage of an antidot lattice is particularly sensitive to the relative positions of the Fermi level and the antidot potential. A quantum dot lattice, on the other hand, provides the opportunity to study correlated electron physics. We find that its current-voltage characteristics display a voltage threshold, as well as a power law scaling, indicative of collective Coulomb blockade in a disordered background.

Observation of localized states in atomically thin MoS2 field effect transistor

We present electrical transport arid low frequency (1/f) noise measurements on mechanically exfoliated single, In and triLayer MoS2-based FPI devices on Si/SiO2 substrate. We find that tie electronic states hi MoS2 are localized at low temperatures (T) and conduction happens through variable range hopping (VRH). A steep increase of 1/f noise with decreasing T, typical for localized regime was observed in all of our devices. From gate voltage dependence of noise, we find that the noise power is inversely proportional to square of the number density (proportional to 1/n(2)) for a wide range of T, indicating number density fluctuations to be the dominant source of 1/f noise in these MoS2 FETs.

AIM-Spice Integration of a Recursive Model for Threshold Voltage Shift in Thin Film Transistors

Non-crystalline semiconductor based thin film transistors are the building blocks of large area electronic systems. These devices experience a threshold voltage shift with time due to prolonged gate bias stress. In this paper we integrate a recursive model for threshold voltage shift with the open source BSIM4V4 model of AIM-Spice. This creates a tool for circuit simulation for TFTs. We demonstrate the integrity of the model using several test cases including display driver circuits.

Quantum simulation using fidelity-profile optimization

Experimental quantum simulation of a Hamiltonian H requires unitary operator decomposition (UOD) of its evolution unitary U = exp(-iHt) in terms of native unitary operators of the experimental system. Here, using a genetic algorithm, we numerically evaluate the most generic UOD (valid over a continuous range of Hamiltonian parameters) of the unitary operator U, termed fidelity-profile optimization. The optimization is obtained by systematically evaluating the functional dependence of experimental unitary operators (such as single-qubit rotations and time-evolution unitaries of the system interactions) to the Hamiltonian (H) parameters. Using this technique, we have solved the experimental unitary decomposition of a controlled-phase gate (for any phase value), the evolution unitary of the Heisenberg XY interaction, and simulation of the Dzyaloshinskii-Moriya (DM) interaction in the presence of the Heisenberg XY interaction. Using these decompositions, we studied the entanglement dynamics of a Bell state in the DM interaction and experimentally verified the entanglement preservation procedure of Hou et al. Ann. Phys. (N.Y.) 327, 292 (2012)] in a nuclear magnetic resonance quantum information processor.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of Delta E-t approximate to 0.3 eV and with a density of state distribution as D-t(Et-j) = D-t0 exp(-Delta E-t/kT) with D-t0 = 5.02 x 10(11) cm(-2) eV(-1). Such a model is useful for developing simulation tools for circuit design. (C) 2014 AIP Publishing LLC.

Hardware Accelerator for 3D Method of Moments based Parasitic Extraction

A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a low-rank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-mu m CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

Inductively coupled reactive ion etching studies on sputtered yttria stabilized zirconia thin films in SF6, Cl-2, and BCl3 chemistries

Downscaling of yttria stabilized zirconia (YSZ) based electrochemical devices and gate oxide layers requires successful pattern transfer on YSZ thin films. Among a number of techniques available to transfer patterns to a material, reactive ion etching has the capability to offer high resolution, easily controllable, tunable anisotropic/isotropic pattern transfer for batch processing. This work reports inductively coupled reactive ion etching studies on sputtered YSZ thin films in fluorine and chlorine based plasmas and their etch chemistry analyses using x-ray photoelectron spectroscopy. Etching in SF6 plasma gives an etch rate of 7 nm/min chiefly through physical etching process. For same process parameters, in Cl-2 and BCl3 plasmas, YSZ etch rate is 17 nm/min and 45 nm/min, respectively. Increased etch rate in BCl3 plasma is attributed to its oxygen scavenging property synergetic with other chemical and physical etch pathways. BCl3 etched YSZ films show residue-free and smooth surface. The surface atomic concentration ratio of Zr/Y in BCl3 etched films is closer to as-annealed YSZ thin films. On the other hand, Cl-2 etched films show surface yttrium enrichment. Selectivity ratio of YSZ over silicon (Si), silicon dioxide (SiO2) and silicon nitride (Si3N4) are 1:2.7, 1:1, and 1:0.75, respectively, in BCl3 plasma. YSZ etch rate increases to 53 nm/min when nonoxygen supplying carrier wafer like Si3N4 is used. (C) 2015 American Vacuum Society.

Suspended core-shell Pt-PtOx nanostructure for ultrasensitive hydrogen gas sensor

High sensitivity gas sensors are typically realized using metal catalysts and nanostructured materials, utilizing non-conventional synthesis and processing techniques, incompatible with on-chip integration of sensor arrays. In this work, we report a new device architecture, suspended core-shell Pt-PtOx nanostructure that is fully CMOS-compatible. The device consists of a metal gate core, embedded within a partially suspended semiconductor shell with source and drain contacts in the anchored region. The reduced work function in suspended region, coupled with builtin electric field of metal-semiconductor junction, enables the modulation of drain current, due to room temperature Redox reactions on exposure to gas. The device architecture is validated using Pt-PtO2 suspended nanostructure for sensing H-2 down to 200 ppb under room temperature. By exploiting catalytic activity of PtO2, in conjunction with its p-type semiconducting behavior, we demonstrate about two orders of magnitude improvement in sensitivity and limit of detection, compared to the sensors reported in recent literature. Pt thin film, deposited on SiO2, is lithographically patterned and converted into suspended Pt-PtO2 sensor, in a single step isotropic SiO2 etching. An optimum design space for the sensor is elucidated with the initial Pt film thickness ranging between 10 nm and 30 nm, for low power (< 5 mu W), room temperature operation. (C) 2015 AIP Publishing LLC.