A current error space vector based hysteresis controller with constant switching frequency and simple online boundary computation for VSI fed IM drive

This paper proposes a simple current error space vector based hysteresis controller for two-level inverter fed Induction Motor (IM) drives. This proposed hysteresis controller retains all advantages of conventional current error space vector based hysteresis controllers like fast dynamic response, simple to implement, adjacent voltage vector switching etc. The additional advantage of this proposed hysteresis controller is that it gives a phase voltage frequency spectrum exactly similar to that of a constant switching frequency space vector pulse width modulated (SVPWM) inverter. In this proposed hysteresis controller the boundary is computed online using estimated stator voltages along alpha and beta axes thus completely eliminating look up tables used for obtaining parabolic hysteresis boundary proposed in. The estimation of stator voltage is carried out using current errors along alpha and beta axes and steady state model of induction motor. The proposed scheme is simple and capable of taking inverter upto six step mode operation, if demanded by drive system. The proposed hysteresis controller based inverter fed drive scheme is simulated extensively using SIMULINK toolbox of MATLAB for steady state and transient performance. The experimental verification for steady state performance of the proposed scheme is carried out on a 3.7kW IM.

Dodecagonal space vector diagram using cascaded H-Bridge inverters

This paper proposes the development of dodecagonal (12-sided) space vector diagrams from cascaded H-Bridge inverters. As already reported in literatures, dodecagonal space vector diagrams have many advantages over conventional hexagonal ones. Some of them include the absence of 6n±1, (n=odd) harmonics from the phase voltage, and the extension of the linear modulation range. In this paper, a new power circuit is proposed for generating multiple dodecagons in the space vector plane. It consists of two cascaded H-Bridge cells fed from asymmetric dc voltage sources. It is shown that, with proper PWM timing calculation and placement of active and zero vectors, a very high quality of sine-wave can be produced. At the same time, the switching frequency of individual cells can be reduced substantially. Detailed PWM analysis, one design example and an elaborate simulation study is presented to support the proposed idea.

Analytical Study of Low-Field Diffusive Transport in Highly Asymmetric Bilayer Graphene Nanoribbon

We present a simplified theory of carrier backscattering coefficient in a twofold degenerate asymmetric bilayer graphene nanoribbon (BGN) under the application of a low static electric field. We show that for a highly asymmetric BGN(Delta = gamma), the density of states in the lower subband increases more that of the upper, in which Delta and gamma are the gap and the interlayer coupling constant, respectively. We also demonstrate that under the acoustic phonon scattering regime, the formation of two distinct sets of energy subbands signatures a quantized transmission coefficient as a function of ribbon width and provides an extremely low carrier reflection coefficient for a better Landauer conductance even at room temperature. The well-known result for the ballistic condition has been obtained as a special case of the present analysis under certain limiting conditions which forms an indirect validation of our theoretical formalism.

An asymmetric cascaded H-Bridge inverters for generating 12-sided polygonal space vector diagrams for Motor drives

A new topology of asymmetric cascaded H-Bridge inverter is presented in this paper It consists of two cascaded H-bridge cells per phase. They are fed from isolated dc sources having a dc bus ratio of 1:0.366. Out of many space vectors possible from this circuit, only those are chosen that lie on 12-sided polygons. Thus, the overall space vector diagram produced by this circuit consists of multiple numbers of 12-sided polygons. With a proper PWM timing calculations based on these selected space vectors, it is possible to eliminate all the 6n +/- 1, (n = odd) harmonics from the phase voltage under all operating conditions. The switching frequency of individual H-Bridge cells is also substantially low. Extensive experimental results have been presented in this paper to validate the proposed concept.

Photo-Defined Electrically Assisted Etching Method for Metal Stencil Fabrication

Metal stencils are well known in electronics printing application such as for dispensing solder paste for surface mounting, printing embedded passive elements in multilayer structures, etc. For microprinting applications using stencils, the print quality depends on the smoothness of the stencil aperture and its dimensional accuracy, which in turn are invariably related to the method used to manufacture the stencils. In this paper, fabrication of metal stencils using a photo-defined electrically assisted etching method is described. Apertures in the stencil were made in neutral electrolyte using three different types of impressed current, namely, dc, pulsed dc, and periodic pulse reverse (PPR). Dimensional accuracy and wall smoothness of the etched apertures in each of the current waveforms were compared. Finally, paste transfer efficiency of the stencil obtained using PPR was calculated and compared with those of a laser-cut electropolished stencil. It is observed that the stencil fabricated using current in PPR waveform has better dimensional accuracy and aperture wall smoothness than those obtained with dc and pulsed dc. From the paste transfer efficiency experiment, it is concluded that photo-defined electrically assisted etching method can provide an alternate route for fabrication of metal stencils for future microelectronics printing applications.

A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating V(dc)/2 where V(dc) is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of V(dc)/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of V(dc)/2, switch less compared to the H-bridges, which operate at a lower voltage level of V(dc)/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions.

Performance Analysis of TCP Uploads in WLANs with Multiple Rates

Throughput analysis of bulk TCP downloads in cases where all WLAN stations are associated at the same rate with the AP is available in the literature. In this paper,we extend the analysis to TCP uploads for the case of multirate associations. The approach is based on a two-dimensional semi- Markov model for the number of backlogged stations. Analytical results are in excellent agreement with simulations performed using QUALNET 4.5.

Impact of Energy Expenditure Rate Constraints on the performance of Multihop Wireless Mesh Networks

In this article we study the problem of joint congestion control, routing and MAC layer scheduling in multi-hop wireless mesh network, where the nodes in the network are subjected to maximum energy expenditure rates. We model link contention in the wireless network using the contention graph and we model energy expenditure rate constraint of nodes using the energy expenditure rate matrix. We formulate the problem as an aggregate utility maximization problem and apply duality theory in order to decompose the problem into two sub-problems namely, network layer routing and congestion control problem and MAC layer scheduling problem. The source adjusts its rate based on the cost of the least cost path to the destination where the cost of the path includes not only the prices of the links in it but also the prices associated with the nodes on the path. The MAC layer scheduling of the links is carried out based on the prices of the links. We study the e�ects of energy expenditure rate constraints of the nodes on the optimal throughput of the network.

Reliable Routing in Sensor Networks

In sensor networks, routing algorithms should be designed such that packet losses due to wireless links are reduced.In this paper, we present a ”potential”-based routing scheme to find routes with high packet delivery ratios. The basic idea is to define a scalar potential value at each node in the network and forward data to the neighbour with the highest potential.For a simple 2-relay network, we propose a potential function that takes into account wireless channel state. Markov-chain based analysis provides analytical expressions for packet delivery ratio. Considerable improvement can be observed compared to a channel-state-oblivious policy. This motivates us to define a channel-state-dependent potential function in a general network context. Simulations show that for a relatively slowly changing wireless network, our approach can provide up to 20% better performance than the commonly- used shortest-hop-count-based routing.

Simulation Blocks for TOSSIM-T2"

We develop several hardware and software simulation blocks for the TinyOS-2 (TOSSIM-T2) simulator. The choice of simulated hardware platform is the popular MICA2 mote. While the hardware simulation elements comprise of radio and external flash memory, the software blocks include an environment noise model, packet delivery model and an energy estimator block for the complete system. The hardware radio block uses the software environment noise model to sample the noise floor.The packet delivery model is built by establishing the SNR-PRR curve for the MICA2 system. The energy estimator block models energy consumption by Micro Controller Unit(MCU), Radio,LEDs, and external flash memory. Using the manufacturer’s data sheets we provide an estimate of the energy consumed by the hardware during transmission, reception and also track several of the MCUs states with the associated energy consumption. To study the effectiveness of this work, we take a case study of a paper presented in [1]. We obtain three sets of results for energy consumption through mathematical analysis, simulation using the blocks built into PowerTossim-T2 and finally laboratory measurements. Since there is a significant match between these result sets, we propose our blocks for T2 community to effectively test their application energy requirements and node life times.

Dynamically Reconfigurable Regular Expression Matching Architecture

Regular Expressions are generic representations for a string or a collection of strings. This paper focuses on implementation of a regular expression matching architecture on reconfigurable fabric like FPGA. We present a Nondeterministic Finite Automata based implementation with extended regular expression syntax set compared to previous approaches. We also describe a dynamically reconfigurable generic block that implements the supported regular expression syntax. This enables formation of the regular expression hardware by a simple cascade of generic blocks as well as a possibility for reconfiguring the generic blocks to change the regular expression being matched. Further,we have developed an HDL code generator to obtain the VHDL description of the hardware for any regular expression set. Our optimized regular expression engine achieves a throughput of 2.45 Gbps. Our dynamically reconfigurable regular expression engine achieves a throughput of 0.8 Gbps using 12 FPGA slices per generic block on Xilinx Virtex2Pro FPGA.