148 resultados para Semiconductor device manufacture


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This paper reports an improvement in Pt/n-GaN metal-semiconductor (MS) Schottky diode characteristics by the introduction of a layer of HfO2 (5 nm) between the metal and semiconductor interface. The resulting Pt/HfO2/n-GaN metal-insulator-semiconductor (MIS) Schottky diode showed an increase in rectification ratio from 35.9 to 98.9(@ 2V), increase in barrier height (0.52 eV to 0.63eV) and a reduction in ideality factor (2.1 to 1.3) as compared to the MS Schottky. Epitaxial n-type GaN films of thickness 300nm were grown using plasma assisted molecular beam epitaxy (PAMBE). The crystalline and optical qualities of the films were confirmed using high resolution X-ray diffraction and photoluminescence measurements. Metal-semiconductor (Pt/n-GaN) and metal-insulator-semiconductor (Pt/HfO2/n-GaN) Schottky diodes were fabricated. To gain further understanding of the Pt/HfO2/GaN interface, I-V characterisation was carried out on the MIS Schottky diode over a temperature range of 150 K to 370 K. The barrier height was found to increase (0.3 eV to 0.79 eV) and the ideality factor decreased (3.6 to 1.2) with increase in temperature from 150 K to 370 K. This temperature dependence was attributed to the inhomogeneous nature of the contact and the explanation was validated by fitting the experimental data into a Gaussian distribution of barrier heights. (C) 2015 Author(s).

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High-kappa TiO2 thin films have been fabricated using cost effective sol-gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO2 films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400 degrees C, retaining its structural integrity up to 1000 degrees C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance-voltage (C-V) characteristics of the films annealed at 400 degrees C exhibited a high value of dielectric constant (similar to 34). Further, frequency dependent C-V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO2/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent `s'=0.85). A low leakage current density of 3.6 x 10(-7) A/cm(2) at 1 V was observed for the films annealed at 600 degrees C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-kappa materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and AID. The results also suggest that the high value of dielectric constant kappa obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology. (C) 2015 Elsevier Ltd. All rights reserved.

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Polyaniline and graphene oxide composite on activated carbon cum reduced graphene oxide-supported supercapacitor electrodes are fabricated and electrochemically characterized in a three-electrode cell assembly. Attractive supercapacitor performance, namely high-power capability and cycling stability for graphene oxide/polyaniline composite, is observed owing to the layered and porous-polymeric-structured electrodes. Based on the materials characterization data in a three-electrode cell assembly, 1 V supercapacitor devices are developed and performance tested. A comparative study has also been conducted for polyaniline and graphene oxide/polyaniline composite-based 1 V supercapacitors for comprehending the synergic effect of graphene oxide and polyaniline. Graphene oxide/polyaniline composite-based capacitor that exhibits about 100 F g(-1) specific capacitance with faradaic efficiency in excess of 90% has its energy and power density values of 14 Wh kg(-1) and 72 kW kg(-1), respectively. Cycle-life data for over 1000 cycles reflect 10% capacitance degradation for graphene oxide/polyaniline composite supercapacitor.

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In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

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Shallow-trench isolation drain extended pMOS (STI-DePMOS) devices show a distinct two-stage breakdown. The impact of p-well and deep-n-well doping profile on breakdown characteristics is investigated based on TCAD simulations. Design guidelines for p-well and deep-n-well doping profile are developed to shift the onset of the first-stage breakdown to a higher drain voltage and to avoid vertical punch-through leading to early breakdown. An optimal ratio between the OFF-state breakdown voltage and the ON-state resistance could be obtained. Furthermore, the impact of p-well/deep-n-well doping profile on the figure of merits of analog and digital performance is studied. This paper aids in the design of STI drain extended MOSFET devices for widest safe operating area and optimal mixed-signal performance in advanced system-on-chip input-output process technologies.

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In the last few years, there has been remarkable progress in the development of group III-nitride based materials because of their potential application in fabricating various optoelectronic devices such as light emitting diodes, laser diodes, tandem solar cells and field effect transistors. In order to realize these devices, growth of device quality heterostructures are required. One of the most interesting properties of a semiconductor heterostructure interface is its Schottky barrier height, which is a measure of the mismatch of the energy levels for the majority carriers across the heterojunction interface. Recently, the growth of non-polar III-nitrides has been an important subject due to its potential improvement on the efficiency of III-nitride-based opto-electronic devices. It is well known that the c-axis oriented optoelectronic devices are strongly affected by the intrinsic spontaneous and piezoelectric polarization fields, which results in the low electron-hole recombination efficiency. One of the useful approaches for eliminating the piezoelectric polarization effects is to fabricate nitride-based devices along non-polar and semi-polar directions. Heterostructures grown on these orientations are receiving a lot of focus due to enhanced behaviour. In the present review article discussion has been carried out on the growth of III-nitride binary alloys and properties of GaN/Si, InN/Si, polar InN/GaN, and nonpolar InN/GaN heterostructures followed by studies on band offsets of III-nitride semiconductor heterostructures using the x-ray photoelectron spectroscopy technique. Current transport mechanisms of these heterostructures are also discussed.

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Self-assembled InN quantum dots (QDs) were grown on Si(111) substrate using plasma assisted molecular beam epitaxy (PA-MBE). Single-crystalline wurtzite structure of InN QDs was confirmed by X-ray diffraction. The dot densities were varied by varying the indium flux. Variation of dot density was confirmed by FESEM images. Interdigitated electrodes were fabricated using standard lithography steps to form metal-semiconductor-metal (MSM) photodetector devices. The devices show strong infrared response. It was found that the samples with higher density of InN QDs showed lower dark current and higher photo current. An explanation was provided for the observations and the experimental results were validated using Silvaco Atlas device simulator.

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In this text we present the design of a wearable health monitoring device capable of remotely monitoring health parameters of neonates for the first few weeks after birth. The device is primarily aimed at continuously tracking the skin temperature to indicate the onset of hypothermia in newborns. A medical grade thermistor is responsible for temperature measurement and is directly interfaced to a microcontroller with an integrated bluetooth low energy radio. An inertial sensor is also present in the device to facilitate breathing rate measurement which has been discussed briefly. Sensed data is transferred securely over bluetooth low energy radio to a nearby gateway, which relays the information to a central database for real time monitoring. Low power optimizations at both the circuit and software levels ensure a prolonged battery life. The device is packaged in a baby friendly, water proof housing and is easily sterilizable and reusable.

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We demonstrate all inorganic, robust, cost-effective, spin-coated, two-terminal capacitive memory metal-oxide nanoparticle-oxide-semiconductor devices with cadmium telluride nanoparticles sandwiched between aluminum oxide phosphate layers to form the dielectric memory stack. Using a novel high-speed circuit to decouple reading and writing, experimentally measured memory windows, programming voltages, retention times, and endurance are comparable with or better than the two-terminal memory devices realized using other fabrication techniques.

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We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.

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In this work, polymer diode performance was analyzed by using nickel as anode electrode from two kinds of nickel as starting materials, namely nickel wire Ni{B} and nickel nano-particle Ni{N}. Metal electrode surface roughness and grain morphology were investigated by atomic force microscope and scanning electron microscope, respectively. Current-voltage (I-V) and capacitance-voltage (C-V) characteristics were measured for the fabricated device at room temperature. Obtained result from the current-voltage characteristics shows an increment in the current density for nickel nano-particle top electrode device. The increase in the current density could be due to a reduction in built-in voltage at P3HT/Ni{N} interface.

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An efficient buffer layer scheme has been designed to address the issue of curvature management during metalorganic chemical vapour deposition growth of GaN on Si (111) substrate. This is necessary to prevent cracking of the grown layer during post-growth cooling down from growth temperature to room temperature and to achieve an allowable bow (<40 m) in the wafer for carrying out lithographic processes. To meet both these ends simultaneously, the stress evolution in the buffer layers was observed carefully. The reduction in precursor flow during the buffer layer growth provided better control over curvature evolution in the growing buffer layers. This has enabled the growth of a suitable high electron mobility transistor (HEMT) stack on 2'' Si (111) substrate of 300 m thickness with a bow as low as 11.4 m, having a two-dimensional electron gas (2DEG) of mobility, carrier concentration, and sheet resistance values 1510 cm(2)/V-s, 0.96 x 10(13)/cm(2), and 444 /, respectively. Another variation of similar technique resulted in a bow of 23.4 m with 2DEG mobility, carrier concentration, and sheet resistance values 1960 cm(2)/V-s, 0.98 x 10(13)/cm(2), and 325 /, respectively.

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The design and synthesis is reported of 7-(9H-carbazol-9-yl)-4-methylcoumarin (Cz-Cm), comprising a carbazole donor moiety and a 4-methylcoumarin acceptor unit, for use in a blue organic light-emitting diode. A detailed solid state, theoretical and spectroscopic study was performed to understand the structure-property relationships. The material exhibits deep-blue emission and high photoluminescence quantum yield both in solution and in a doped matrix. A deep-blue electroluminescence emission at 430nm, a maximum brightness of 292cdm(-2) and an external quantum efficiency of 0.4% was achieved with a device configured as follows: ITO/NPD (30nm)/TCTA (20nm)/CzSi(10nm)/10wt% Cz-Cm:DPEPO (10nm)/TPBI (30nm)/LiF (1nm)/Al ITO=indium tin oxide, NPD=N,N-di(1-naphthyl)-N,N-diphenyl-(1,1-biphenyl)-4,4-diamine, TCTA=tris(4-carbazoyl-9-ylphenyl)amine, CzSi=9-(4-tert-butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole, DPEPO=bis2-(diphenylphosphino)phenyl]ether oxide, TPBI=1,3,5-tris(N-phenylbenzimidazol-2-yl)benzene].