A Compact Model incorporating Quantum Effects for Ultra-Thin-Body Double-Gate MOSFETs

We propose a compact model which predicts the channel charge density and the drain current which match quite closely with the numerical solution obtained from the Full-Band structure approach. We show that, with this compact model, the channel charge density can be predicted by taking the capacitance based on the physical oxide thickness, as opposed to C-eff, which needs to be taken when using the classical solution.

Behaviour of power MOSFETs at cryogenic temperatures

In this paper an investigation is reported on Siemens-power-metal-oxide-semiconductor (SIPMOS) transistors of both p and n channel types, for their suitability for cryogenic applications. The drain characteristics, temperature dependence of Rds(on) and switching behaviour have been studied in the temperature range 4.2 – 300 K in BSS91 and BSS92 MOSFETs. The experiments reveal that these types of power transistors are well suited for operations down to ≈ 30 K. However, below 30 K the operating characteristics make them unsuitable for application. This arises because of carrier freeze-out in the n− region on the substrate, which forms a drain.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (V-T) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (phi(s)) to a value phi(sT) necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that phi(sT). The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3 x 10(-15)-5 x 10(17)/cm(3). Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature. (C) 2012 Elsevier B.V. All rights reserved.

Nonquasi-static charge model for common double-gate MOSFETs adapted to gate oxide thickness asymmetry

With the unique quasi-linear relationship between the surface potentials along the channel, recently we have proposed a quasi-static terminal charge model for common double-gate MOSFETs, which might have asymmetric gate oxide thickness. In this brief, we extend this concept to develop the nonquasi-static (NQS) charge model for the same by solving the governing continuity equations. The proposed NQS model shows good agreement against TCAD simulations and appears to be useful for efficient circuit simulation.

Small signal Nonquasi-Static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry

We present a physics-based closed form small signal Nonquasi-static (NQS) model for a long channel Common Double Gate MOSFET (CDG) by taking into account the asymmetry that may prevail between the gate oxide thickness. We use the unique quasi-linear relationship between the surface potentials along the channel to solve the governing continuity equation (CE) in order to develop the analytical expressions for the Y parameters. The Bessel function based solution of the CE is simplified in form of polynomials so that it could be easily implemented in any circuit simulator. The model shows good agreement with the TCAD simulation at-least till 4 times of the cut-off frequency for different device geometries and bias conditions.

Concept of Crossover point and its application on Threshold Voltage definition for Undoped-Body Transistors

As the conventional MOSFETs scaling is approaching the limit imposed by short channel effects, Double Gate (DG) MOS transistors are appearing as the most feasible andidate in terms of technology in sub-45nm technology nodes. As the short channel effect in DG transistor is controlled by the device geometry, undoped or lightly doped body, is used to sustain the channel. There exits a disparity in threshold voltage calculation criteria of undoped-body symmetric double gate transistors which uses two definitions, one is potential based and the another is charge based definition. In this paper, a novel concept of "crossover point" is introduced, which proves that the charge-based definition is more accurate than the potential based definition. The change in threshold voltage with body thickness variation for a fixed channel length is anomalous as predicted by, potential based definition while it is monotonous for change based definition. The threshold voltage is then extracted from drain currant versus gate voltage characteristics using linear extrapolation and "Third Derivative of Drain-Source Current" method or simply "TD" method. The trend of threshold voltage variation is found some in both the cases which support charge-based definition.

Integrated CMOS Gas Sensors

We present a low power gas sensor system on CMOS platform consisting of micromachined polysilicon microheater, temperature controller circuit, resistance readout circuit and SnO2 transducer film. The design criteria for different building blocks of the system is elaborated The microheaters are optimized for temperature uniformity as well as static and dynamic response. The electrical equivalent model for the microheater is derived by extracting thermal and mechanical poles through extensive laser doppler vibrometer measurements. The temperature controller and readout circuit are realized on 130nm CMOS technology The temperature controller re-uses the heater as a temperature sensor and controls the duty cycle of the waveform driving the gate of the power MOSFET which supplies heater current. The readout circuit, with subthreshold operation of the MOSFETs, is based oil resistance to time period conversion followed by frequency to digital converter Subthreshold operatin of MOSFETs coupled with sub-ranging technique, achieves ultra low power consumption with more than five orders of magnitude dynamic range RF sputtered SnO2 film is optimized for its microstructure to achive high sensitivity to sense LPG gas.

'Wet N2O oxidation' process and interface state density characterization of nanoscale nitrided SiO2 for flash memory application

In this paper we first present the 'wet N2O' furnace oxidation process to grow nitrided tunnel oxides in the thickness range 6 to 8 nm on silicon at a temperature of 800 degrees C. Electrical characteristics of MOS capacitors and MOSFETs fabricated using this oxide as gate oxide have been evaluated and the superior features of this oxide are ascertained The frequency response of the interface states, before and after subjecting the MOSFET gate oxide to constant current stress, is studied using a simple analytical model developed in this work.

Quantum Threshold Voltage Modeling of Short Channel Quad Gate Silicon Nanowire Transistor

In this paper, a physically based analytical quantum linear threshold voltage model for short channel quad gate MOSFETs is developed. The proposed model, which is suitable for circuit simulation, is based on the analytical solution of 3-D Poisson and 2-D Schrodinger equation. Proposed model is fully validated against the professional numerical device simulator for a wide range of device geometries and also used to analyze the effect of geometry variation on the threshold voltage.

Indian Nanoelectronics Users Program An Outreach Vehicle to Expedite Nanoelectronics Research in India

The worldwide research in nanoelectronics is motivated by the fact that scaling of MOSFETs by conventional top down approach will not continue for ever due to fundamental limits imposed by physics even if it is delayed for some more years. The research community in this domain has largely become multidisciplinary trying to discover novel transistor structures built with novel materials so that semiconductor industry can continue to follow its projected roadmap. However, setting up and running a nanoelectronics facility for research is hugely expensive. Therefore it is a common model to setup a central networked facility that can be shared with large number of users across the research community. The Centres for Excellence in Nanoelectronics (CEN) at Indian Institute of Science, Bangalore (IISc) and Indian Institute of Technology, Bombay (IITB) are such central networked facilities setup with funding of about USD 20 million from the Department of Information Technology (DIT), Ministry of Communications and Information Technology (MCIT), Government of India, in 2005. Indian Nanoelectronics Users Program (INUP) is a missionary program not only to spread awareness and provide training in nanoelectronics but also to provide easy access to the latest facilities at CEN in IISc and at IITB for the wider nanoelectronics research community in India. This program, also funded by MCIT, aims to train researchers by conducting workshops, hands-on training programs, and providing access to CEN facilities. This is a unique program aiming to expedite nanoelectronics research in the country, as the funding for projects required for projects proposed by researchers from around India has prior financial approval from the government and requires only technical approval by the IISc/ IITB team. This paper discusses the objectives of INUP, gives brief descriptions of CEN facilities, the training programs conducted by INUP and list various research activities currently under way in the program.

Multilevel inverters for low-power application

Multilevel inverters are an attractive solution in the medium-voltage and high-power applications. However in the low-power range also it can be a better solution compared to two-level inverters, if MOSFETs are used as devices switching in the order of 100 kHz. The effect of clamping diodes in the diode-clamped multilevel inverters play an important role in determining its efficiency. Power loss introduced by the reverse recovery of MOSFET body diode prohibits the use of MOSFET in hard-switched inverter legs. A technique of avoiding reverse recovery loss of MOSFET body diode in a three-level neutral point clamped inverter is suggested. The use of multilevel inverters topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps in reducing the size of the inverter. This study elaborates the trade-off analysis to quantify the suitability of multilevel inverters in the low-power applications. Advantages of using a MOSFET-based three-level diode-clamped inverter for a PM motor drive and UPS systems are discussed.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Signal-Powered Low-Drop-Diode Equivalent Circuit for Full-Wave Bridge Rectifier

Piezoelectric-device-based vibration energy harvesting requires a rectifier for conversion of input ac to usable dc form. Power loss due to diode drop in rectifier is a significant fraction of the already low levels of harvested power. The proposed circuit is a low-drop-diode equivalent, which mimics a diode using linear region-operated MOSFET. The proposed diode equivalent is powered directly from input signal and requires no additional power supply for its control. Power used by the control circuit is kept at a bare minimum to have an overall output power improvement. Diode equivalent was used to replace the four diodes in a full-wave bridge rectifier, which is the basic full- wave rectifier and is a part of the more advanced rectifiers like switch-only and bias-flip rectifiers. Simulation in 130-nm technology and experiment with discrete components show that a bridge rectifier with the proposed diode provides a 30-169% increase in output power extracted from piezoelectric device, as compared to a bridge rectifier with diode-connected MOSFETs. The bridge rectifier with the proposed diode can extract 90% of the maximum available power from an ideal piezoelectric device-bridge rectifier circuit. Setting aside the constraint of power loss, simulations indicate that diode drop as low as 10 mV at 38 mu A can be achieved.