A Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.

High On/Off ratio memristive switching of manganite/cuprate bilayer by interfacial magnetoelectricity

Memristive switching serves as the basis for a new generation of electronic devices. Memristors are two-terminal devices in which the current is turned on and off by redistributing point defects, e.g., vacancies, which is difficult to control. Memristors based on alternative mechanisms have been explored, but achieving both the high On/Off ratio and the low switching energy desirable for use in electronics remains a challenge. Here we report memristive switching in a La_(0.7)Ca_(0.3)MnO_(3)/PrBa_(2)Cu_(3)O_(7) bilayer with an On/Off ratio greater than 103 and demonstrate that the phenomenon originates from a new type of interfacial magnetoelectricity. Using results from firstprinciples calculations, we show that an external electric-field induces subtle displacements of the interfacial Mn ions, which switches on/off an interfacial magnetic “dead” layer, resulting in memristive behavior for spin-polarized electron transport across the bilayer. The interfacial nature of the switching entails low energy cost about of a tenth of atto Joule for write/erase a “bit”. Our results indicate new opportunities for manganite/cuprate systems and other transition-metal-oxide junctions in memristive applications.

Synchronization of Heteroclinic Circuits Through Learning in Chains of Neural Motifs

The synchronization of oscillatory activity in networks of neural networks is usually implemented through coupling the state variables describing neuronal dynamics. In this study we discuss another but complementary mechanism based on a learning process with memory. A driver network motif, acting as a teacher, exhibits winner-less competition (WLC) dynamics, while a driven motif, a learner, tunes its internal couplings according to the oscillations observed in the teacher. We show that under appropriate training the learner motif can dynamically copy the coupling pattern of the teacher and thus synchronize oscillations with the teacher. Then, we demonstrate that the replication of the WLC dynamics occurs for intermediate memory lengths only. In a unidirectional chain of N motifs coupled through teacher-learner paradigm the time interval required for pattern replication grows linearly with the chain size, hence the learning process does not blow up and at the end we observe phase synchronized oscillations along the chain. We also show that in a learning chain closed into a ring the network motifs come to a consensus, i.e. to a state with the same connectivity pattern corresponding to the mean initial pattern averaged over all network motifs.