A Methodology to Emulate Single Event Upsets in Flip-Flops using FPGAs through Partial Reconfiguration and Instrumentation

This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the FFs. The method proposed in this paper is a hybrid approach that combines FPGA partial reconfiguration and extra logic added to the circuit under test, without modifying its operation. This approach has been integrated into a fault-injection platform, named NESSY (Non intrusive ErrorS injection SYstem), developed by our research group. Finally, this paper includes results on a Virtex-5 FPGA demonstrating the validity of the method on the ITC’99 benchmark set and a Feed-Forward Equalization (FFE) filter. In comparison with other approaches in the literature, this methodology reduces the resource consumption introduced to carry out the fault injection in FFs, at the cost of adding very little time overhead (1.6 �μs per fault).

A functional representation of almost isometries

For each quasi-metric space X we consider the convex lattice SLip(1)(X) of all semi-Lipschitz functions on X with semi-Lipschitz constant not greater than 1. If X and Y are two complete quasi-metric spaces, we prove that every convex lattice isomorphism T from SLip(1)(Y) onto SLip(1)(X) can be written in the form Tf = c . (f o tau) + phi, where tau is an isometry, c > 0 and phi is an element of SLip(1)(X). As a consequence, we obtain that two complete quasi-metric spaces are almost isometric if, and only if, there exists an almost-unital convex lattice isomorphism between SLip(1)(X) and SLip(1) (Y).