Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

Synchronous products of rewrite systems (extended version)

We present and formalize a concept of synchronous product for rewrite systems, and also a corresponding concept for general transition systems, used as semantics for the former. A series of examples shows their practical usefulness: for the strategic control of systems, and for modular specification and verification.