A Methodology to Emulate Single Event Upsets in Flip-Flops using FPGAs through Partial Reconfiguration and Instrumentation

This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the FFs. The method proposed in this paper is a hybrid approach that combines FPGA partial reconfiguration and extra logic added to the circuit under test, without modifying its operation. This approach has been integrated into a fault-injection platform, named NESSY (Non intrusive ErrorS injection SYstem), developed by our research group. Finally, this paper includes results on a Virtex-5 FPGA demonstrating the validity of the method on the ITC’99 benchmark set and a Feed-Forward Equalization (FFE) filter. In comparison with other approaches in the literature, this methodology reduces the resource consumption introduced to carry out the fault injection in FFs, at the cost of adding very little time overhead (1.6 �μs per fault).

Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

Reconfigurable computing for Monte Carlo simulations: results and prospects of the Janus project

We describe Janus, a massively parallel FPGA-based computer optimized for the simulation of spin glasses, theoretical models for the behavior of glassy materials. FPGAs (as compared to GPUs or many-core processors) provide a complementary approach to massively parallel computing. In particular, our model problem is formulated in terms of binary variables, and floating-point operations can be (almost) completely avoided. The FPGA architecture allows us to run many independent threads with almost no latencies in memory access, thus updating up to 1024 spins per cycle. We describe Janus in detail and we summarize the physics results obtained in four years of operation of this machine; we discuss two types of physics applications: long simulations on very large systems (which try to mimic and provide understanding about the experimental non equilibrium dynamics), and low-temperature equilibrium simulations using an artificial parallel tempering dynamics. The time scale of our non-equilibrium simulations spans eleven orders of magnitude (from picoseconds to a tenth of a second). On the other hand, our equilibrium simulations are unprecedented both because of the low temperatures reached and for the large systems that we have brought to equilibrium. A finite-time scaling ansatz emerges from the detailed comparison of the two sets of simulations. Janus has made it possible to perform spin glass simulations that would take several decades on more conventional architectures. The paper ends with an assessment of the potential of possible future versions of the Janus architecture, based on state-of-the-art technology.

Implementación sobre FPGA de un algoritmo de compresión de imágenes hiperespectrales bajo el estándar CCSDS 123.0-B-1

A lo largo de la historia, nuestro planeta ha atravesado numerosas y diferentes etapas. Sin embargo, desde finales del cretácico no se vivía un cambio tan rápido como el actual. Y a la cabeza del cambio, nosotros, el ser humano. De igual manera que somos la causa, debemos ser también la solución, y el análisis a gran escala de la tierra está siendo un punto de interés para la comunidad científica en los últimos años. Prueba de ello es que, cada vez con más frecuencia, se lanzan gran cantidad de satélites cuya finalidad es el análisis, mediante fotografías, de la superficie terrestre. Una de las técnicas más versátiles para este análisis es la toma de imágenes hiperespectrales, donde no solo se captura el espectro visible, sino numerosas longitudes de onda. Suponen, eso sí un reto tecnológico, pues los sensores consumen más energía y las imágenes más memoria, ambos recursos escasos en el espacio. Dado que el análisis se hace en tierra firme, es importante una transmisión de datos eficaz y rápida. Por ello creemos que la compresión en tiempo real mediante FPGAs es la solución idónea, combinando un bajo consumo con una alta tasa de compresión, posibilitando el análisis ininterrumpido del astro en el que vivimos. En este trabajo de fin de grado se ha realizado una implementación sobre FPGA, utilizando VHDL, del estándar CCSDS 123. Este está diseñado para la compresión sin pérdida de imágenes hiperespectrales, y permite una amplia gama de configuraciones para adaptarse de manera óptima a cualquier tipo de imagen. Se ha comprobado exitosamente la validez de la implementación comparando los resultados obtenidos con otras implementaciones (software) existentes. Las principales ventajas que presentamos aquí es que se posibilita la compresión en tiempo real, obteniendo además un rendimiento energético muy prometedor. Estos resultados mejoran notablemente los de una implementación software del algoritmo, y permitirán la compresión de las imágenes a bordo de los satélites que las toman.

Statistical Anomalies of Bitflips in SRAMs to Discriminate SBUs from MCUs

Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.