机械臂惯性矩阵的并行计算

本文在给出一种非递推形式的逆动力学计算公式的基础上，针对机械臂惯性矩阵的计算提出了一种面向Ｏ（ｎ）个处理器的并行算法，并以ＰＵＭＡ５６０机器人的前３个臂为例进行了计算效率分析

On optimal message vector length for block single parallel partition algorithm in a three-dimensional ADI solver

It has long been recognized that many direct parallel tridiagonal solvers are only efficient for solving a single tridiagonal equation of large sizes, and they become inefficient when naively used in a three-dimensional ADI solver. In order to improve the parallel efficiency of an ADI solver using a direct parallel solver, we implement the single parallel partition (SPP) algorithm in conjunction with message vectorization, which aggregates several communication messages into one to reduce the communication costs. The measured performances show that the longest allowable message vector length (MVL) is not necessarily the best choice. To understand this observation and optimize the performance, we propose an improved model that takes the cache effect into consideration. The optimal MVL for achieving the best performance is shown to depend on number of processors and grid sizes. Similar dependence of the optimal MVL is also found for the popular block pipelined method.

MODIFIED DIRECT TWOS-COMPLEMENT PARALLEL ARRAY MULTIPLICATION ALGORITHM FOR COMPLEX MATRIX OPERATION

A direct twos-complement parallel array multiplication algorithm is introduced and modified for digital optical numerical computation. The modified version overcomes the problems encountered in the conventional optical twos-complement algorithm. In the array, all the summands are generated in parallel, and the relevant summands having the same weights are added simultaneously without carries, resulting in the product expressed in a mixed twos-complement system. In a two-stage array, complex multiplication is possible with using four real subarrays. Furthermore, with a three-stage array architecture, complex matrix operation is straightforwardly accomplished. In the experiment, parallel two-stage array complex multiplication with liquid-crystal panels is demonstrated.

Parallel optical negabinary signed-digit computing: algorithm and optical implementation

Negabinary is a component of the positional number system. A complete set of negabinary arithmetic operations are presented, including the basic addition/subtraction logic, the two-step carry-free addition/subtraction algorithm based on negabinary signed-digit (NSD) representation, parallel multiplication, and the fast conversion from NSD to the normal negabinary in the carry-look-ahead mode. All the arithmetic operations can be performed with binary logic. By programming the binary reference bits, addition and subtraction can be realized in parallel with the same binary logic functions. This offers a technique to perform space-variant arithmetic-logic functions with space-invariant instructions. Multiplication can be performed in the tree structure and it is simpler than the modified signed-digit (MSD) counterpart. The parallelism of the algorithms is very suitable for optical implementation. Correspondingly, a general-purpose optical logic system using an electron trapping device is suggested. Various complex logic functions can be performed by programming the illumination of the data arrays without additional temporal latency of the intermediate results. The system can be compact. These properties make the proposed negabinary arithmetic-logic system a strong candidate for future applications in digital optical computing with the development of smart pixel arrays. (C) 1999 Society of Photo-Optical Instrumentation Engineers. [S0091-3286(99)00803-X].

A block SPP algorithm for multidimensional tridiagonal equations with optimal message vector length

A parallel strategy for solving multidimensional tridiagonal equations is investigated in this paper. We present in detail an improved version of single parallel partition (SPP) algorithm in conjunction with message vectorization, which aggregates several communication messages into one to reduce the communication cost. We show the resulting block SPP can achieve good speedup for a wide range of message vector length (MVL), especially when the number of grid points in the divided direction is large. Instead of only using the largest possible MVL, we adopt numerical tests and modeling analysis to determine an optimal MVL so that significant improvement in speedup can be obtained.

Parallel optical negabinary arithmetic based on logic operations

On the basis of signed-digit negabinary representation, parallel two-step addition and one-step subtraction can be performed for arbitrary-length negabinary operands.; The arithmetic is realized by signed logic operations and optically implemented by spatial encoding and decoding techniques. The proposed algorithm and optical system are simple, reliable, and practicable, and they have the property of parallel processing of two-dimensional data. This leads to an efficient design for the optical arithmetic and logic unit. (C) 1997 Optical Society of America.

Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio. (C) 1999 Optical Society of America.

Two-step digit-set-restricted modified signed-digit addition-subtraction algorithm and its optoelectronic implementation

A novel, to our knowledge, two-step digit-set-restricted modified signed-digit (MSD) addition-subtraction algorithm is proposed. With the introduction of the reference digits, the operand words are mapped into an intermediate carry word with all digits restricted to the set {(1) over bar, 0} and an intermediate sum word with all digits restricted to the set {0, 1}, which can be summed to form the final result without carry generation. The operation can be performed in parallel by use of binary logic. An optical system that utilizes an electron-trapping device is suggested for accomplishing the required binary logic operations. By programming of the illumination of data arrays, any complex logic operations of multiple variables can be realized without additional temporal latency of the intermediate results. This technique has a high space-bandwidth product and signal-to-noise ratio. The main structure can be stacked to construct a compact optoelectronic MSD adder-subtracter. (C) 1999 Optical Society of America.

Application of the Conjugate Gradient Optimization Algorithm of Neural Network on Laser Machining

在应用激光技术加工复杂曲面时,通常以采样点集为插值点来建立曲面函数,然后实现曲面上任意坐标点的精确定位。人工神经网络的BP算法能实现函数插值,但计算精度偏低,往往达不到插值精确要求,造成较大的加工误差。提出人工神经网络的共轭梯度最优化插值新算法,并通过实例仿真,证明了这种曲面精确定位方法的可行性,从而为激光加工的三维精确定位提供了一种良好解决方案。这种方法已经应用在实际中。

Simulating shock to detonation transition: Algorithm and results

An algorithm based on flux-corrected transport and the Lagrangian finite element method is presented for solving the problem of shock dynamics. It is verified through the model problem of one-dimensional strain elastoplastic shock wave propagation that the algorithm leads to stable, non-oscillatory results. Shock initiation and detonation wave propagation is simulated using the algorithm, and some interesting results are obtained. (C) 1999 Academic Press.

A New Designed Two-Dimensional Bifurcation Parallel-Plate Flow Chamber

解决平行平板流槽每次实验只能观测壁面培养细胞受一种剪应力作用的问题。作者在平行平板流槽的基础上,首次提出了一种改进后的流槽--二维平板分叉流槽。通过数值模拟,给出了流体作定常流动时,流速和壁面剪应力的分布。结果发现,利用这种二维平板分叉流槽可以研究壁面培养的细胞在不同大小剪应力作用下的力学行为。该研究结果为流槽的合理设计和使用,并分析剪应力空间分布对内皮细胞的影响有重要实际意义。

A Label-Free Protein Microfluidic Array for Parallel Immunoassays

A label-free protein microfluidic array for immunoassays based on the combination of imaging ellipsometry and an integrated microfluidic system is presented. Proteins can be patterned homogeneously on substrate in array format by the microfluidic system simultaneously. After preparation, the protein array can be packed in the microfluidic system which is full of buffer so that proteins are not exposed to denaturing conditions. With simple microfluidic channel junction, the protein microfluidic array can be used in serial or parallel format to analyze single or multiple samples simultaneously. Imaging ellipsometry is used for the protein array reading with a label-free format. The biological and medical applications of the label-free protein microfluidic array are demonstrated by screening for antibody–antigen interactions, measuring the concentration of the protein solution and detecting five markers of hepatitis B.