An ultra-low power CMOS random number generator

This paper proposes an ultra-low power CMOS random number generator (RING), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 mu m CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 mu W. This novel circuit is a promising unit for low power system and communication applications. (c) 2007 Elsevier Ltd. All rights reserved.

Effects of anode temperature on working characteristics and performance of a low power arcjet thruster

An arc-heated thruster of 130–800 W input power is tested in a vacuum chamber at pressures lower than 20 Pa with argon or H2–N2 gas mixture as propellant. The time-dependent arc voltage-current curve, outside-surface temperature of the anode nozzle and the produced thrust of the firing arcjet thruster are measured in situ simultaneously, in order to analyze and evaluate the dependence of thruster working characteristics and output properties, such as specific impulse and thrust efficiency, on nozzle temperature.

Plume Parameters and Thruster Properties of a Low Power Arcjet

Abstract. A low power arcjet-thruster of 1 kW-class with gas mixture of H2-N2 or pure argon as the propellant is fired at a chamber pressure about 10 Pa. The nozzle temperature is detected with an infrared pyrometer; a plate set perpendicular to the plume axis and connected to a force sensor is used to measure the thrust; a probe with a tapered head is used for measuring the impact pressure in the plume flow; and a double-electrostatic probe system is applied to evaluate the electron temperature. Results indicate that the high nozzle temperature could adversely affect the conversion from enthalpy to kinetic energy. The plume flow deviates evidently from the LTE condition, and the rarefied-gas dynamic effect should be considered under the high temperature and low-pressure condition in analyzing the experimental phenomena.

Low-Power Super-resolution Readout with Antimony Bismuth Alloy Film as Mask layer

Sb-Bi alloy films are proposed as a new kind of super-resolution mask layer with low readout threshold power. Using the Sb-Bi alloy film as a mask layer and SiN as a protective layer in a read-only memory disc, the super-resolution pits with diameters of 380 nm are read out by a dynamic setup, the laser wavelength is 780 nm and the numerical aperture of pickup lens is 0.45. The effects of the Sb-Bi thin film thickness, laser readout power and disc rotating velocity on the readout signal are investigated. The results show that the threshold laser power of super-resolution readout of the Sb-Bi mask layer is about 0.5 mW, and the corresponding carrier-to-noise ratio is about 20 dB at the film thickness of 50 nm. The super-resolution mechanism of the Sb-Bi alloy mask layer is discussed based on its temperature dependence of reflection.

Thermodynamic damage mechanism of transparent films caused by a low-power laser

A new model for analyzing the laser-induced damage process is provided. In many damage pits, the melted residue can been found. This is evidence of the phase change of materials. Therefore the phase change of materials is incorporated into the mechanical damage mechanism of films. Three sequential stages are discussed: no phase change, liquid phase change, and gas phase change. To study the damage mechanism and process, two kinds of stress have been considered: thermal stress and deformation stress. The former is caused by the temperature gradient and the latter is caused by high-pressure drive deformation. The theory described can determine the size of the damage pit. (c) 2006 Optical Society of America.

Thermo-optic variable optical attenuator with low power consumption fabricated on silicon-on-insulator by anisotropic chemical etching

A thermo-optic Mach-Zehnder (MZ) variable optical attenuator based on silicon waveguides with a large cross section was designed and fabricated on silicon-on-insulator (SOI) wafer. Multimode interferometers were used as power splitters and combiners in the MZ structure. In order to achieve a smooth interface, anisotropic chemical etching of silicon was used to fabricate the waveguides. Isolating grooves were introduced to reduce power consumption and device length. The device has a low power consumption of 210 mW and a response time of 50 mus. (C) 2004 Society of Photo-Optical Instrumentation Engineers.

Low power 2 x 2 thermo-optic SOI waveguide switch fabricated by anisotropy chemical etching

A 2 x 2 thermo-optic (TO) Mach-Zehnder (MZ) switch based on silicon waveguides with large cross section was designed and fabricated on silicon-on-insulator (SOI) wafer. The multi-mode interferometers (MMI) were used as power splitter and combiner in MZ structure. In order to get smooth interface, anisotropy chemical wet-etching of silicon was used to fabricate the waveguides instead of dry-etching. Additional grooves were introduced to reduce power consumption. The device has a low switching power of 235 mW and a switching speed of 60 mus. (C) 2004 Elsevier B.V. All rights reserved.

Low power-consumption and high response frequency thermo-optic variable optical Attenuators based on silicon-on-insulator materials

A novel silicon-on-insulator thermo-optic variable optical attenuator with isolated grooves based on a multimode interference coupler principle is fabricated by the inductive coupled plasma etching technology. The maximum fibre-to-fibre insertion loss is lower than 2.2 dB, the dynamic attenuation range is from 0 to 30 dB in the wavelength range 1500-1600 nm, and the maximum power consumption is only 140 mW. The response frequency of the fabricated variable optical attenuator is about 30 kHz. Compared to the variable optical attenuator without isolated grooves, the maximum power consumption decreases more than 220 mW, and the response frequency rises are more than 20 kHz.

Fabrication and analysis of 2x2 thermo-optic SOI waveguide switch with low power consumption and fast response by anisotropy chemical etching

A low power consumption 2 x 2 thermo-optic switch with fast response was fabricated on silicon-on-insulator by anisotropy chemical etching. Blocking trenches were etched on both sides of the phase-shifting arms to shorten device length and reduce power consumption. Thin top cladding layer was grown to reduce power consumption and switching time. The device showed good characteristics, including a low switching power of 145 mW and a fast switching speed of 8 +/- 1 mus, respectively. Two-dimensional finite element method was applied to simulate temperature field in the phase-shifting arm instead of conventional one-dimensional method. According to the simulated result, a new two-dimensional index distribution of phase-shifting arm was determined. Consequently finite-difference beam propagation method was employed to simulate the light propagation in the switch, and calculate the power consumption as well as the switching speed. The experimental results were in good agreement with the theoretical estimations. (C) 2004 Elsevier B.V. All rights reserved.

A novel ultra low power temperature sensor for UHF RFID tag chip

A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs are not needed. The sensor is realized in a standard 0.18 mu m CMOS process, and the area is only 0.2mm(2). The accuracy of the temperature sensor is +/- 1 degrees C after calibration. The power consumption of the sensor is only 0.9 mu W.

A Low Power Baseband Chain for CMMB Application

This paper presents experimental results of an analog baseband circuit for China Multimedia Mobile Broadcasting (CMMB) direct conversion receiver in 0.35um SiGe BiCMOS process. It is the first baseband of CMMB RFIC reported so far. A 8(th)-order chebyshev low pass filter (LPF) with calibration system is used in the analog baseband circuit, the filter provides 0.5 dB passband ripple and -35 dB attenuation at 6MHz with the cutoff frequency at 4MHz, the calibration of filter is reported to achieve the bandwidth accuracy of 3%. The baseband variable gain amplifier (VGA) achieves more than 40 dB gain tuning with temperature compensation. In addition, A DC offset cancellation circuit is also introduced to remove the offset from layout and self-mixing, and the remaining offset voltage and current consumption are only 6mV and 412uA respectively. Implemented in a 0.35um SiGe technology with 1.1 mm(2) die size, this tuner baseband achieves OIP3 of 25.5 dBm and dissipate 16.4 mA under 2.8-V supply.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

Design of Low Power Multi-Standard Active-RC Filter for WLAN and DVB-H

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.