基于Yices对时间自动机的有界模型检测

为了避免在有界模型检测过程中对变量进行布尔编码以及对时间自动机模型中的时钟进行预处理,给出一个利用SMT(satisfiability modulo theories)工具进行的对时间自动机进行有界模型检测的方法。该方法将时间自动机模型直接转换成SMT工具可识别的逻辑公式,利用SMT工具可求解包含有整数型和实数型变量逻辑公式的能力来进行模型检测。实验结果表明,对于某些可达性性质的验证,该方法的效率有一定的优势。

When is `partial' adequate? A logic-based proof technique using partial specifications

A technique is presented for ascertaining when a (finite-state) partial process specification is adequate, in the sense of being specified enough, for contexts in which it is to be used. The method relies on the automatic generation of a modal formula from the partial specification; if the remainder of the network satisfies this formula, then any process that meets the specification is guaranteed to ensure correct behavior of the overall system. Using the results, the authors develop compositional proof rules for establishing the correctness of networks of parallel processes and illustrate their use with several examples

Applicability Range of Stoneys Formula and Modified Formulas for a Film/Substrate Bilayer

In addition to the layer thickness and effective Young’s modulus, the impact of the kinematic assumptions, interfacial condition, in-plane force, boundary conditions, and structure dimensions on the curvature of a film/substrate bilayer is examined. Different models for the analysis of the bilayer curvature are compared. It is demonstrated in our model that the assumption of a uniform curvature is valid only if there is no in-plane force. The effects of boundary conditions and structure dimensions, which are not-fully-included in previous models are shown to be significant. Three different approaches for deriving the curvature of a film/substrate bilayer are presented, compared, and analyzed. A more comprehensive study of the conditions regarding the applicability of Stoney’s formula and modified formulas is presented.

Extended Stoney'S Formula For A Film-Substrate Bilayer With The Effect Of Interfacial Slip

The curvature-stress relation is studied for a film-substrate bilayer with the effect of interfacial slip and compared with that of an ideal interface without interfacial slip. The interfacial slip together with the dimensions, elastic and interfacial properties of the film and substrate layers can cause a significant deviation of curvature-stress relation from that with an ideal interface. The interfacial slip also results in the so-called free edge effect that the stress, constraint force, and curvature vary dramatically around the free edges. The constant curvature as predicted by Stoney's formula and the Timoshenko model of an ideal interface is no longer valid for a bilayer with a nonideal interface. The models with the assumption of an ideal interface can also lead to an erroneous evaluation on the true stress state inside a bilayer with a nonideal interface. The extended Stoney's formula incorporating the effects of both the layer dimensions and interfacial slip is presented.

Modified formula of Malus' law for Glan-Taylor polarizing prisms

A simple three-axis model has been developed, which has been successfully applied to the analysis of the light transmittance in spatial incident angle and the simulation of modified formula of Malus' law for Glan-Taylor prisms. Our results indicate that the fluctuations on the cosine squared curve are due to specific misalignments between the axis of the optical system, the optical axis of the prism and the mechanical axis (rotation axis) of prism, which results in the fact that different initial relative location of the to-be-measured-prism in the testing system corresponds to different shape of Malus' law curve. Methods to get absolutely smooth curve are proposed. This analysis is available for other kinds of Glan-type prisms. (C) 2004 Elsevier B.V. All rights reserved.

Parallel optical negabinary arithmetic based on logic operations

On the basis of signed-digit negabinary representation, parallel two-step addition and one-step subtraction can be performed for arbitrary-length negabinary operands.; The arithmetic is realized by signed logic operations and optically implemented by spatial encoding and decoding techniques. The proposed algorithm and optical system are simple, reliable, and practicable, and they have the property of parallel processing of two-dimensional data. This leads to an efficient design for the optical arithmetic and logic unit. (C) 1997 Optical Society of America.

Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio. (C) 1999 Optical Society of America.

Logic-operated mathematical morphology and its optical implementation

A more powerful tool for binary image processing, i.e., logic-operated mathematical morphology (LOMM), is proposed. With LOMM the image and the structuring element (SE) are treated as binary logical variables, and the MULTIPLY between the image and the SE in correlation is replaced with 16 logical operations. A total of 12 LOMM operations are obtained. The optical implementation of LOMM is described. The application of LOMM and its experimental results are also presented. (C) 1999 Optical Society of America.

Code conversion from signed-digit to complement representation based on look-ahead optical logic operations

We present, for the first time to our knowledge, a generalized lookahead logic algorithm for number conversion from signed-digit to complement representation. By properly encoding the signed-digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quarternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using an electron-trapping device is employed and experimental results are shown. This optical module is suitable for implementing complex logic functions in the form of the sum of the product. The algorithm and architecture are compatible with a general-purpose optoelectronic computing system. (C) 2001 Society of Photo-Optical Instrumentation Engineers.

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Landauer-Buttiker formula for time-dependent transport through resonant-tunneling structures: A nonequilibrium Green's function approach

A nonequilibrium Green's-function formalism is employed to study the time-dependent transport through resonant-tunneling structures. With this formalism, we derive a time-dependent Landauer-Buttiker formula that guarantees current conservation and gauge invariance. Furthermore, we apply the formula to calculate the response behaviors of the resonant-tunneling structures in the presence of rectangular-pulse and harmonic-modulation fields. The results show that the displacement current plays the role of retarding the tunneling current.

Photonic switch and NOT logic gate based on the hybrid integration of a GaAsVCSEL and a GaAs MISS

The hybrid integrated photonic switch and not logic gate based on the integration of a GaAs VCSEL (Vertical Cavity Surface Emitting Lasers) and a MISS (Metal-Insulator-Semiconductor Switches) device are reported. The GaAs VCSEL is fabricated by selective etching and selective oxidation. The Ultra-Thin semi-Insulating layer (UTI) of the GaAs MISS is formed by using oxidation of A1As that is grown by MBE. The accurate control of UTI and the processing compatibility between VCSEL and MISS are solved by this procedure. Ifa VCSEL is connected in series with a MISS, the integrated device can be used as a photonic switch, or a light amplifier. A low switching power (10 mu W) and a good on-off ratio (17 dB contrast) have been achieved. If they are connected in parallel, they perform a photonic NOT gate operation.