A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz.

分布计算环境中实现对象互操作的联邦交易模型

本文依据分布计算环境（ＤＣＥ）中所提供的目录服务并结合开放分布处理（ＯＤＰ）所提供的交易服务（ＴｒａｄｉｎｇＳｅｒｖｉｃｅｓ），提出了实现分布计算环境中对象互操作的联邦交易模型。给出了该交易模型在ＤＣＥ中的实现结构模型。

ODP系统中的联邦交易模型

In this paper we present a federated trading model for the trading services of ODP, A federation constract is used to document the agreement between two federating traders. The federation constract consists of import constract and export constract. We discuss the constituent of the model based on the five viewpoints of ODP.