Simple lattice Boltzmann model for traffic flows

A lattice Boltzmann model with 5-bit lattice for traffic flows is proposed. Using the Chapman-Enskog expansion and multi-scale technique, we obtain the higher-order moments of equilibrium distribution function. A simple traffic light problem is simulated by using the present lattice Boltzmann model, and the result agrees well with analytical solution.

Sedimentary records of water environment in lake Chaohu in the Yangtze delta region, China

Three lacustrine core samples were collected from Chaohu lake in December 2002 in the Yangtze delta region. The grain sizes were analyzed using a Laser Analyzer to obtain grain-size parameters. Sediment geochronology was determined in radioisotopes Cs-137 and the average sedimentary rates are 0.29cm.a(-1), 0.35 cm.a(-1) and 0.24cm-a(-1) in Cores C 1, C2 and C3, respectively. The grain-size parameters of the deposits vary regularly with the fluctuation of hydrodynamics. From 1950s to the beginning of 20th century, coarse-grained sediment was deposited, suggesting strong hydraulic conditions and high water-level periods with much precipitation; from the start of 20(th) century to latter half of 18(th) century, fine-grained sediment was deposited, indicating that weak hydraulic conditions and low water-level periods with less precipitation; before the first half of 18(th) century, coarse-grained sediment was deposited, suggesting great velocity of flow and high water-level periods of more precipitation.

Records of enchytraeidae (Clitellata) from the People's Republic of China

Eleven species of terrestrial and aquatic Enchytraeidae are reported from southeastern China. Fridericia multisegmentata and Enchytraeus athecatus are new to science, while most of the others are recorded from the country for the first time.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.