Pulse compression by filamentation in argon with an acoustic optical programmable dispersive filter for predispersion compensation

We have experimentally demonstrated pulses 0.4 mJ in duration smaller than 12 fs; with an excellent spatial beam profile by self-guided propagation in argon. The original 52 fs pulses from the chirped pulsed amplification laser system are first precompressed to 32 fs by inserting an acoustic optical programmable dispersive filter instrument into the laser system for spectrum reshaping and dispersion compensation, and the pulse spectrum is subsequently broadened by filamentation in an argon cell. By using chirped mirrors for post-dispersion compensation, the pulses are successfully compressed to smaller than 12 fs.

A low-cost CMOS programmable temperature

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature T-th can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature T-th variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 mu m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature T(th)s from 45-120 degrees C with a 5 degrees C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm(2) and power consumption is 3.1 mu A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

Pulse Compression by Filamentation in Argon with an Acoustic Optical Programmable Dispersive Filter for Predispersion Compensation

We have experimentally demonstrated pulses 0.4 mJ in duration smaller than 12 fs with an excellent spatial beam profile by self-guided propagation in argon. The original 52 fs pulses from the chirped pulsed amplification laser system are first precompressed to 32 fs by inserting an acoustic optical programmable dispersive filter instrument into the laser system for spectrum reshaping and dispersion compensation, and the pulse spectrum is subsequently broadened by filamentation in an argon cell. By using chirped mirrors for post-dispersion compensation, the pulses are successfully compressed to smaller than 12 fs.

Active phase control and frequency chirp effects on supercontinuum generation in high birefringence photonic crystal fiber

An acoustic-optics programmable dispersive filter (AOPDF) was first employed to actively control the linearly polarized femtosecond pump pulse frequency chirp for supercontinuum (SC) generation in a high birefringence photonic crystal fiber (PCF). By accurately controlling the second order phase distortion and polarization direction of incident pulses, the output SC spectrum can be tuned to various spectral energy distributions and bandwidths. The pump pulse energy and bandwidth are preserved in our experiment. It is found that SC with broader bandwidth can be generated with positive chirped pump pulses except when the chirp value is larger than the optimal value, and the same optimal value exists for the pump pulses polarized along the two principal axes. With optimal positive chirp, more than 78% of the pump energy can be transferred to below 750 nm. Otherwise, negative chirp will weaken the blue-shift broadening and the SC bandwidth. (C) 2007 Elsevier B.V. All rights reserved.

Generation of 17-TW 23-fs pulses with a two-stage Ti : Sapphire amplifier at repetition rate 10 Hz

We have developed a two-stage Ti:sapphire amplifier system which can produce 17-TW/23-fs pulses at a repetition rate 10 MHz. A birefringent plate is used in the regenerative amplifier to alleviate gain narrowing, while an all-reflective cylindrical-mirror-based pulse stretcher and an acousto-optic programmable dispersive filter (AOPDF) are used to compensate for the higher order dispersion of the system.

Parasitic lasing suppression in high gain femtosecond petawatt Ti: sapphire amplifier

New parasitic lasing suppression techniques are developed and high gain amplification is demonstrated in a petawatt level Ti:sapphire amplifier based on the chirped pulse amplification (CPA) scheme. Cladding the large aperture Ti: sapphire with refractive-index matched liquid doped with absorber suppresses the transverse lasing. The acousto-optic programmable dispersive filter (AOPDF) is used to realize side-lobe suppression in the temporal profile of the compressed pulse. The 800 nm laser output with peak power of 0.89 PW and pulse width of 29.0 fs is demonstrated. (c) 2007 Optical Society of America.

适合于小飞机防撞系统的机载小型激光测距仪

报道了一种重量轻、功耗低、适合于小飞机防撞系统应用的小型激光测距仪。系统基于脉冲激光测距原理，采用905nm半导体脉冲激光器、电感升压式偏置高压电源和可编程逻辑器件（PLD），研制出重量不大于100g，功耗不大于625mW，测量范围100m，盲区3．0m，分辨率±1m的机载小型激光测距仪。实验测试结果表明，其各项技术性能指标符合无人驾驶小飞机防撞系统的应用要求。

星载激光测距仪的高精度时间间隔测量单元

高精度时间间隔测量单元(TIU)是星载激光测距仪的关键部件。基于现场可编程门阵列(FPGA)研制出了满足星载要求的高精度、高集成度时间间隔测量单元。该单元采用数字计数法结合数字延迟线插入法的技术,在0.5～10 km的测量距离范围内,时间分辨率为500 ps。通过地面检测,在全程范围内保持了良好的线性度,标准偏差小于270 ps。该单元同时具备测量脉冲回波宽度的能力,可以获取目标的脉冲展宽信息。由于单元选用的元器件都具有航天产品性能,因此其设计和技术指标可满足星载激光测距仪的应用。

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

The design and verification of FPGA CAD toolset

This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.