Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.

兰州重离子加速器冷却储存环主环二极铁电源设计；Design of main ring dipole power supply for Heavy Ion Research Facility in Lanzhou-Cooling Storage Ring

主环二极铁电源是兰州重离子加速器冷却储存环(HIRFL-CSR)工程的关键设备和指标要求最高的一台电源,采用了独特的拓扑和控制策略。为满足峰值功率3.15MW(3kA,1.45kV)的输出能力和快脉冲要求,采用了晶闸管整流并联脉宽调制补偿单元的主电路拓扑结构和特殊的控制方式,这套综合方案确保电源满足了全部技术指标。本文介绍了该拓扑结构的原理和优势,讨论了为满足±2×10-4的跟踪误差的要求而采用的控制拓扑和双基准给定的原理,并简介了调试过程和近年来的运行和改进情况。

HIRFL-CSR二极磁铁电源的研制；Development of Power Supply for HIRFL-CSR Dipole Magnet

研制了兰州重离子加速器冷却储存环(HIRFL-CSR)二极磁铁电源,提出了一种基于晶闸管相控整流技术和IGBT脉宽调制(PWM)变换技术的同步加速器二极磁铁电源的设计方案,分析、仿真了其工作原理,并设计、生产了1套完整的电源样机。经现场试验、长期运行及测试,电流稳定度<±5×10-5/8h,跟踪精度<±2×10-4,电流纹波<1×10-5。该方案满足HIRFL-CSR二极磁铁对电源技术指标的要求。

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Welding of Al alloy plates using a novel high-average-power pulsed CO2 laser

A novel high-average-power pulsed CO2 laser with a unique electrode structure is presented. The operation of a 5-kW transverse-flow CO2 laser with the preionized pulse-train switched technique results in pulsation of the laser power, and the average laser power is about 5 kW. The characteristic of this technique is switching the preionized pulses into pulse trains so as to use the small preionized power (hundreds of watts) to control the large main-discharge power (tens of kilowatts). By this means, the cost and the complexity of the power supply are greatly reduced. The welding of LF2, LF21, LD2, and LY12 aluminum alloy plates has been successfully achieved using this laser. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

Welding of Al alloy plates using a novel high-average-power pulsed CO2 laser

A novel high-average-power pulsed CO2 laser with a unique electrode structure is presented. The operation of a 5-kW transverse-flow CO2 laser with the preionized pulse-train switched technique results in pulsation of the laser power, and the average laser power is about 5 kW. The characteristic of this technique is switching the preionized pulses into pulse trains so as to use the small preionized power (hundreds of watts) to control the large main-discharge power (tens of kilowatts). By this means, the cost and the complexity of the power supply are greatly reduced. The welding of LF2, LF21, LD2, and LY12 aluminum alloy plates has been successfully achieved using this laser. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

A novel technique for predicting ionizing radiation effects of commercial MOS devices

A nondestructive selection technique for predicting ionizing radiation effects of commercial metal-oxide-semiconductor (MOS) devices has been put forward. The basic principle and application details of this technique have been discussed. Practical application for the 54HC04 and 54HC08 circuits has shown that the predicted radiation-sensitive parameters such as threshold voltage, static power supply current and radiation failure total dose are consistent with the experimental results obtained only by measuring original electrical parameters. It is important and necessary to choose suitable information parameters. This novel technique can be used for initial radiation selection of some commercial MOS devices.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A direct-conversion mixer with a DC-offset cancellation for WLAN

This paper presents a 5GHz double-balanced mixer with DC-offset cancellation circuit for direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard. The analog feedback loop is used, to eliminate the DC-offset at the output of the double-balanced mixer. The test results show that the mixer with DC-offset cancellation circuit has voltage conversion gain of 9.5dB at 5.15GHz, noise figure of 13.5dB, IIP3 of 7.6 dBm, 1.73mV DC-offset voltage and 67mW power with 3.3-V power supply. The DC-offset cancellation circuit has less than 0.1mm(2) additional area and 0.3mW added power dissipation. The direct conversion WLAN receiver has been implemented in a 0.35 mu m SiGe BiCMOS technology.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

Neuro-Stimulus Chip with Photodiodes Array for Sub-retinal Implants

A prototype neuro-stimulus chip for sub-retinal implants in blind patients affected by Age-related Macular Degeneration (AMD) or Retinitis Pigmentosa (RP) is presented in this paper. This retinal prosthetic chip was designed to replace the degenerated photoreceptor cells, and in order to stimulate directly the remaining healthy layers of retinal neurons. The current stimulus circuits are monolithic integrated with photodiodes (PD) array, which can convert the illumination on the eyes into bi-phasic electrical pulses. In addition, a novel charge cancellation circuit is used to discharge the electrodes for medical safty. The prototype chip is designed and fabricated in HJTC 0.18 mu m N-well CMOS 1P6M Mix-signal process, with a +/- 2.5 V dual voltage power supply.