6 resultados para Output voltage regulation

em Chinese Academy of Sciences Institutional Repositories Grid Portal


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An three phase adjustable output voltage rectifier with constant power flow based on waveform gap patching principle is resented. By patching the gapes in the phase currents in parallel way as well as the ripple of the output voltage in series way, it implements the constant power flow from the three-phase line to the DC output without using any line frequency (and its harmonics) energy storage components. Principally, by treating only 22.4% power of the needed power output, this rectifier can supply constant power flow with adjustable output voltages without bring about any harmonic interferences to the power utility and achieve unite power factor.

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We report on the realization of ZnO homojunction light-emitting diodes (LEDs) fabricated by metalorganic chemical vapor deposition on (0001) ZnO bulk substrate. The p-type ZnO epilayer was formed by nitrogen incorporation using N2O gas as oxidizing and doping sources. Distinct electroluminescence (EL) emissions in the blue and yellow regions were observed at room temperature by the naked eye under forward bias. The EL peak energy coincided with the photoluminescence peak energy of the ZnO epilayer, suggesting that the EL emissions emerge from the ZnO epilayer. In addition, the current-voltage and light output-voltage characteristics of ZnO homojunction LEDs have also been studied. (c) 2006 American Institute of Physics.

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This paper proposes an ultra-low power CMOS random number generator (RING), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 mu m CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 mu W. This novel circuit is a promising unit for low power system and communication applications. (c) 2007 Elsevier Ltd. All rights reserved.

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This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

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在线性电位器的电路设计中、电路前后级的输出和输入阻抗的影响以及使用与安装不当都可能引入非线性,造成电路和控制系统的精度达不到要求。为此,针对电位器的调节输出电压、限定调节范围、负载等效阻抗、细调等几种典型电路中的传递函数与非线性响应,通过实验给出了线性和非线性输出响应曲线。阐述了实际应用中如何避免和减少非线性的影响。

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Optimized AlGaN/AlN/GaN high electron mobility transistors (HEMTs) structures were grown on 2-in semi-insulating (SI) 6H-SiC substrate by metal-organic chemical vapor deposition (MOCVD). The 2-in. HEMT wafer exhibited a low average sheet resistance of 305.3 Omega/sq with a uniformity of 3.85%. The fabricated large periphery device with a dimension of 0.35 pm x 2 nun demonstrated high performance, with a maximum DC current density of 1360 mA/mm, a transconductance of 460 mS/mm, a breakdown voltage larger than 80 V, a current gain cut-off frequency of 24 GHz and a maximum oscillation frequency of 34 GHz. Under the condition of continuous-wave (CW) at 9 GHz, the device achieved 18.1 W output power with a power density of 9.05 W/mm and power-added-efficiency (PAE) of 36.4%. While the corresponding results of pulse condition at 8 GHz are 22.4 W output power with 11.2 W/mm power density and 45.3% PAE. These are the state-of-the-art power performance ever reported for this physical dimension of GaN HEMTs based on SiC substrate at 8 GHz. (c) 2008 Elsevier Ltd. All rights reserved.