Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier

Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.

Performing Fast Addition and Multiplication by Transferring Single Electrons

This paper proposes novel fast addition and multiplication circuits that are based on non-binary redundant number systems and single electron (SE) devices. The circuits consist of MOSFET-based single-electron (SE) turnstiles. We use the number of electrons to represent discrete multiple-valued logic states and we finish arithmetic operations by controlling the number of electrons transferred. We construct a compact PD2,3 adder and a 12x12bit multiplier using the PD2,3 adder. The speed of the adder can be as high as 600MHz with 400nW power dissipation. The speed of the adder is regardless of its operand length. The proposed circuits have much smaller transistors than conventional circuits.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

Performance of an embedded optical vector matrix multiplication processor architecture

An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl's law is used to analyse the hybrid opto-electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.

BRST invariant theory of a generalized 1+1 Dimensional nonlinear sigma model with topological term

We give a generalized Lagrangian density of 1 + 1 Dimensional O( 3) nonlinear sigma model with subsidiary constraints, different Lagrange multiplier fields and topological term, find a lost intrinsic constraint condition, convert the subsidiary constraints into inner constraints in the nonlinear sigma model, give the example of not introducing the lost constraint. N = 0, by comparing the example with the case of introducing the lost constraint, we obtain that when not introducing the lost constraint, one has to obtain a lot of various non-intrinsic constraints. We further deduce the gauge generator, give general BRST transformation of the model under the general conditions. It is discovered that there exists a gauge parameter beta originating from the freedom degree of BRST transformation in a general O( 3) nonlinear sigma model, and we gain the general commutation relations of ghost field.

伴随法在潮汐和海温数值计算中的应用研究

变分数据同化中的伴随法可实现数值模型与观测数据的拟合。随着物理海洋数值计算和数值预报业务的不断发展，其具有广阔的应用前景。本文主要研究关于伴随数据同化的有关理论及其在物理海洋数值模型中的应用。本文介绍了变分伴随数据同化的基本原理，从模型方程的连续和离散形式出发讨论采用两种不同的方法推导伴随方程，一是拉格朗日乘子（Lagrange multiplier）法；二是基于泛函的Gateaux微分概念的方法，这里简称Gateaux微分法。文中讨论了导出离散伴随模型方程和目标函数梯度的两种不同途径，其中一种途径是由连续的正模型得到连续的伴随模型及连续的目标函数梯度表达式，然后再对伴随模型和目标函数梯度进行差分离散（简称“伴随的差分”）；另外一种途径是由离散的正模型直接导出离散的伴随模型及梯度表达式（简称“差分的伴随”）。目前尽管人们比较一致的看法是应该采用后一种途径，即建立伴随模型系统应该采用“差分的伴随”，但对由这两种途径建立的伴随系统的相互关系，人们探讨的并不多。本文利用了简单的模型对该问题进行了研究。另外，对有关初始猜测和伴随优化系统的多解性问题进行了探讨。本文着重研究并实现了利用伴随法优化非线性潮汐模型的开边界条件。其中采用的二维非线性浅水模型既考虑非线性底磨擦和侧向粘性涡动混合，又包括非线性平流项；离散伴随模型的建立是基于ADI格式（不受CFL条件限制），改善了变分伴随数据同化过程中计算量和计算存储问题，使之减小若干倍（约5～7倍），从而使得模式适于业务化的需求，具有实用价值；同化过程中使用的观测数据既包括常规验潮站水位观测资料，又包括TOPEX/POSEIDON卫星测高数据。实测数据同化数值试验表明，开边界条件的最优控制对数值计算结果有一定程度的改进。本文还探讨了将伴随法应用于海表面温度（SST）的数值预报中。其中采用的SST数值预报模型是基于国家“七五”期间科技攻关项目《中国近海海表面温度短期数值预报模式》。文中利用船舶报SST观测数据进行伴随数据同化试验，以优化初始场，其结果是比较满意的，表明变分数据同化对改进SST数值预报的效果是比较明显的，将伴随法引入中国海域SST数值预报业务化中是可行的。本文最后讨论了伴随数据同化中尚待深入研究的问题，着重指出了在物理海洋学领域开展二阶伴随模式应用研究的内容和必要性。