A power-saving scheme for IEEE 802.11 Ad hoc networks

In the Wireless Local Area Networks (WLANs), the terminals are often powered by battery, so the power-saving performance of the wireless network card is a very important issue. For IEEE 802.11 Ad hoc networks, a power-saving scheme is presented in Medium Access Control (MAC) layer to reduce the power consumption by allowing the nodes enter into the sleep mode, but the scheme is based on Time-Drive Scheme (TDS) whose power-saving efficiency becomes lower and lower with the network load increasing. This paper presented a novel energy-saving mechanism, called as Hybrid-Drive Scheme (HDS), which introduces into a Message.-Drive Scheme (MDS) and combines MDS with the conventional TDS. The MDS, could obtain high efficiency when the load is heavy; meanwhile the TDS has high efficiency when the network load is small. The analysis shows that the proposed HDS could obtain high energy-efficiency whether the network load is light or heavy and have higher energy-saving efficiency than conventional scheme in the IEEE 802.11 standard.

A two-step backoff scheme for improving the performance of the IEEE 802.11 distributed coordination function

This paper describes the binary exponential backoff mechanism of 802.11 distributed coordination function (DCF), and introduces some methods of modifying the backoff scheme. Then a novel backoff scheme, called Two-step Backoff scheme, is presented and illustrated. The simulation process in OPNET environment has been described also. At last, the analysis and simulation results show that the Two-step backoff scheme can enhance the performance of the IEEE 802.11 DCF.

A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12×1.25 mm~2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85℃ converges within±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.

A new frequency offset estimation for OFDM-based systems

A new carrier frequency offset estimation scheme in orthogonal frequency division multiplexing (OFDM) is proposed. The scheme includes coarse frequency offset estimation and fine frequency offset estimation. The coarse frequency offset estimation method we present is a improvement of Zhang's method. The estimation range of the new method is as large as the overall signal-band width. A new fine frequency offset estimation algorithm is also discussed in this paper. The new algorithm has a better performance than the Schmidl's algorithm. The system we use to calculate and simulate is based on the high rate WLAN standard adopted by the IEEE 802.11 stanidardization group. Numerical results are presented to demonstrate the performance of the proposed algorithm.

A new frequency offset estimation for OFDM-Based systems

A-new-carrier-frequency offset estimation scheme in orthogonal frequency division multiplexing (OFDM) is proposed. The scheme includes coarse frequency offset estimation and fine frequency offset estimation. The coarse frequency offset estimation method we present is a improvement of Zhang's method. The estimation range of the new method is as large as the overall signal-band width. A new fine frequency offset estimation algorithm is also discussed in this paper. The new algorithm has a better performance than the Schmidt's algorithm. The system we use to calculate and simulate is based on the high rate WLAN standard adopted by the IEEE 802.11 standardization group. Numerical results are presented to demonstrate the performance of the proposed algorithm.

A direct-conversion mixer with a DC-offset cancellation for WLAN

This paper presents a 5GHz double-balanced mixer with DC-offset cancellation circuit for direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard. The analog feedback loop is used, to eliminate the DC-offset at the output of the double-balanced mixer. The test results show that the mixer with DC-offset cancellation circuit has voltage conversion gain of 9.5dB at 5.15GHz, noise figure of 13.5dB, IIP3 of 7.6 dBm, 1.73mV DC-offset voltage and 67mW power with 3.3-V power supply. The DC-offset cancellation circuit has less than 0.1mm(2) additional area and 0.3mW added power dissipation. The direct conversion WLAN receiver has been implemented in a 0.35 mu m SiGe BiCMOS technology.

Design of Low Power Multi-Standard Active-RC Filter for WLAN and DVB-H

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.

AN EFFICIENT ITERATIVE DFT-BASED CHANNEL ESTIMATION FOR MIMO-OFDM SYSTEMS ON MULTIPATH CHANNELS

In this paper, an efficient iterative discrete Fourier transform (DFT) -based channel estimator with good performance for multiple-input and multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems such as IEEE 802.11n which retain some sub-carriers as null sub-carriers (or virtual carriers) is proposed. In order to eliminate the mean-square error (MSE) floor effect existed in conventional DFT-based channel estimators, we proposed a low-complexity method to detect the significant channel impulse response (CIR) taps, which neither need any statistical channel information nor a predetermined threshold value. Analysis and simulation results show that the proposed method has much better performance than conventional DFT-based channel estimators and without MSE floor effect.

植物激素“802”对凤眼莲耐寒及去污能力的影响

叶面喷施“８０２”能提高凤眼莲耐寒和去污能力，“８０２”的喷施浓度以１００ｍｇ／ｌ为宜，但“８０２”不能提高凤眼莲对水温的极端忍受限，水温低于５℃时凤眼莲仍会死亡。

植物激素“802”对凤眼莲耐寒及去污能力的影响

叶面喷施“８０２”能提高凤眼莲耐寒和去污能力，“８０２”的喷施浓度以１００ｍｇ／Ｌ为宜，但“８０２”不能提高凤眼莲对水温的极端忍受限，水温低于５℃时凤眼莲仍会死亡。

Computation of resonant frequencies and quality factors of cavities by FDTD technique and Pade approximation

The finite-difference time domain (FDTD) technique and the Pade approximation with Baker's algorithm are used to calculate the mode frequencies and quality factors of cavities. Comparing with the fast Fourier transformation/Pade method, we find that the Fade approximation and the Baker's algorithm can obtain exact resonant frequencies and quality factors based on a much shorter time record of the FDTD output.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

Implantable Microsystem for Wireless Neural Recording Applications

A prototype microsystem is presented for wireless neural recording application. An inductive link was built for transcutaneous wireless power transfer and data transmission. Total 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 - 5 MHz with a distance of 0-10 mm. The integrated amplifiers were designed with a limited bandwidth for neural signals acquisition. The gain of 60 dB was obtained by preamplifier at 7 Hz - 3 KHz. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments with 0.374 - 2 mW power comsumption and a maximum data rate of 500 Kbps at 100 MHz. All the integrated circuits modules except the power recovery circuit were tested or stimulated under a 3.3 V power supply, and fabricated in standard CMOS processing.