Research on Q-Switched Nd : YAG laser engraving

IN this paper, the engraving process with Q-Switched Nd:YAG laser is investigated. High power density is the pre- requisition to vapor materials, and high repetition rate makes the engraving process highly efficient. An acousto- optic Q-Switch is applied in the cavity of CW 200 W Nd:YAG laser to achieve the high peak power density and the high pulse repetition rate. Different shape craters are formed in a patterned structure on the material surface when the laser beam irradiates on it by controlling power density, pulse repetition rate, pulse quantity and pulse interval. In addition, assisting oxygen gas is used for not only improving combustion to deepen the craters but also removing the plasma that generated on the top of craters. Off-focus length classified as negative and positive has a substantial effect on crater diameters. According to the message of rotating angle positions from material to be engraved and the information of graph pixels from computer, a special graph is imparted to the material by integrating the Q- Switched Nd:YAG laser with the computer graph manipulation and the numerically controlled worktable. The crater diameter depends on laser beam divergence and laser focal length. The crater diameter changes from 50 micrometers to 300 micrometers , and the maximum of crater depth reaches one millimeter.

An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

SBS-based slow light in optical fibers: optimum design considerations for undistorted slow-light signal propagation in steady-state and transient regimes

SPIE

Determination of dispersion and nonlinear coefficients of photonic crystal fibers by degenerated FWM method

使用四波混频测试光子晶体光纤的色散和非线性参数