113 resultados para GATE DIELECTRICS GD2O3

em Chinese Academy of Sciences Institutional Repositories Grid Portal


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Copper phthalocyanine organic thin-film transistors (OTFTs) were fabricated with top-gate geometry and the effects of different gate dielectrics on the transport proper-ties in OTFTs were studied. The mobility was found to be gate voltage dependent and the results showed that besides the charge density in the accumulation layer, the energetic disorder induced by gate dielectrics played an important role in determining the field-effect mobility in OTFTs.

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Stoichiometric gadolinium oxide thin films have been grown on silicon (100) substrates with a low-energy dual ion-beam epitaxial technique. Gadolinium oxide shares Gd2O3 structures although the ratio of gadolinium and oxygen in the film is about 2:1 and a lot of oxygen deficiencies exist. Photoluminescence (PL) measurements have been carried out within a temperature range of 5-300 K. The detailed characters of the PL emission integrated intensity, peak position, and peak width at different temperature were reported and an anomalous photoluminescence behavior was observed. The character of PL emission integrated intensity is similar to that of some other materials such as porous silicon and silicon nanocrystals in silicon dioxide. Four peaks relative to alpha band and beta band were observed also. Therefore we suggest that the nanoclusters with the oxygen deficiencies contribute to the PL emission and the model of singlet-triplet exchange splitting of exciton was employed for discussion. (C) 2003 American Institute of Physics.

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The traditional gate dielectric material Of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.

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Organic thin-film transistor memory devices were realized by inserting a layer of nanoparticles (such as Ag or CaF2) between two Nylon 6 gate dielectrics as the floating gate. The transistor memories were fabricated on glass substrates by full thermal deposition. The transistors exhibit significant hysteresis behavior in current-voltage characteristics, due to the separated Ag or CaF2 nanoparticle islands that act as charge trap centers. The mechanism of the transistor memory operation was discussed.

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Different fluoride materials are used as gate dielectrics to fabricate copper phthalocyanine (CuPc) thin film. transistors (OTFTs). The fabricated devices exhibit good electrical characteristics and the mobility is found to be dependent on the gate voltage from 10(-3) to 10(-1) cm(2) V(-1)s(-1). The observed noticeable electron injection at the drain electrode is of great significance in achieving ambipolar OTFTs. The same method for formation of organic semiconductors and gate dielectric films greatly simplifies the fabrication process. This provides a convenient way to produce high-performance OTFTs on a large scale and should be useful for integration in organic displays.

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Very low hysteresis vanadyl-phthalocyanine/para-sexiphenyl thin-film transistors (TFTs) have been fabricated using benzocyclobutenone (BCBO) derivatives/tantalum pentoxide (Ta2O5)/BCBO triple gate dielectrics. The field effect mobility, on/off current ratio and threshold voltage of organic TFTs are 0.45 cm(2) V-1 s(-1), 3.5 x 10(4) and -6.8 V, respectively. To clarify the mechanism of hysteresis, devices with different dielectrics have been studied. It is found that the bottom BCBO derivatives (contact with a gate electrode) block the electron injection from a gate electrode to dielectrics.

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A novel bilayer photoresist insulator is applied in flexible vanadyl-phthalocyanine (VOPc) organic thin-film transistors (OTFTs). The micron-size patterns of this photoresisit insulator can be directly defined only by photolithography without the etching process. Furthermore, these OTFTs exhibit high field-effect mobility (about 0.8 cm(2)/Vs) and current on/off ratio (about 10(6)). In particular, they show rather low hysteresis (< 1 V). The results demonstrate that this bilayer photoresist insulator can be applied in large-area electronics and in the facilitation of patterning insulators.

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Organic thin film transistors based on pentacene are fabricated by the method of full evaporation. The thickness of insulator film can be controlled accurately, which influences the device operation voltage markedly. Compared to the devices with a single-insulator layer, the electric performance of devices by using a double-insulator as the gate dielectric has good improvement. It is found that the gate leakage current can be reduced over one order of magnitude, and the on-state current can be enhanced over one order of magnitude. The devices with double-insulator layer exhibit field-effect mobility as large as 0.14 cm(2)/Vs and near the zero threshold voltage. The results demonstrate that using proper double insulator as the gate dielectrics is an effective method to fabricate OTFTs with high electrical performance.

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Gadolinium oxide thin films have been prepared on silicon (100) substrates with a low-energy dual ion-beam epitaxial technique. Substrate temperature was an important factor to affect the crystal structures and textures in an ion energy range of 100-500 eV. The films had a monoclinic Gd2O3 structure with preferred orientation ((4) over bar 02) at low substrate temperatures. When the substrate temperature was increased, the orientation turned to (202), and finally, the cubic structure appeared at the substrate temperature of 700 degreesC, which disagreed with the previous report because of the ion energy. The AES studies found that Gadolinium oxide shared Gd2O3 structures, although there were a lot of oxygen deficiencies in the films, and the XPS results confirmed this. AFM was also used to investigate the surface images of the samples. Finally, the electrical properties were presented. (C) 2004 Elsevier B.V. All rights reserved.

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Gadolinium oxide thin films have been prepared on silicon (100) substrates with a low-energy dual ion-beam epitaxial technique. Substrate temperature was an important factor to affect the crystal structures and textures in an ion energy range of 100-500 eV. The films had a monoclinic Gd2O3 structure with preferred orientation ((4) over bar 02) at low substrate temperatures. When the substrate temperature was increased, the orientation turned to (202), and finally, the cubic structure appeared at the substrate temperature of 700 degreesC, which disagreed with the previous report because of the ion energy. The AES studies found that Gadolinium oxide shared Gd2O3 structures, although there were a lot of oxygen deficiencies in the films, and the XPS results confirmed this. AFM was also used to investigate the surface images of the samples. Finally, the electrical properties were presented. (C) 2004 Elsevier B.V. All rights reserved.

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Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta2O5) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode.

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Bottom-contact organic thin-film transistors (BC OTFTs) based on inorganic/organic double gate insulators were demonstrated. The double gate insulators consisted of tantalum pentoxide (Ta2O5) with high dielectric constant (kappa) as the first gate insulator and octadecyltrichlorosilane (OTS) with low kappa as the second gate insulator. The devices have carrier mobilities larger than 10(-2) cm(2)/V s, on/off current ratio greater than 10(5), and the threshold voltage of -14 V, which is threefold larger field-effect mobility and an order of magnitude larger on/off current ratio than the OTFTs with a Ta2O5 gate insulator. The leakage current was decreased from 2.4x10(-6) to 7.4x10(-8) A due to the introduction of the OTS second dielectric layer. The results demonstrated that using inorganic/organic double insulator as the gate dielectric layer is an effective method to fabricate OTFTs with improved electric characteristics.

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In this paper, we briefly summarize two typical morphology characteristics of the self-organized void array induced in bulk of fused silica glass by a tightly focused femtosecond laser beam, such as the key role of high numerical aperture in the void array formation and the concentric-circle-like structure indicated by the top view of the void array. By adopting a physical model which combines the nonlinear propagation of femtosecond laser pulses with the spherical aberration effect (SA) at the interface of two mediums of different refractive indices, reasonable agreements between the simulation results and the experimental results are obtained. By comparing the fluence distributions of the case with both SA and nonlinear effects included and the case with only consideration of SA, we suggest that spherical aberration, which results from the refractive index mismatch between air and fused silica glass, is the main reason for the formation of the self-organized void array. (c) 2008 American Institute of Physics.

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Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

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A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.